commit b873bcc4b399d73f657016cfac4022a9209159c0
author Alex Van Damme <atv@google.com> Tue Oct 29 15:32:46 2024 -0700
committer Alex Van Damme <atv@google.com> Tue Oct 29 15:34:51 2024 -0700
tree 8fc2e6e58bf2773fa614192f2322a768597b0109
parent 61749a810c1c721e350756e4dc81aeec6dfc02e5

Plumb enable signal in TCM128

- Bring the enable signal all the way to the SRAM instances, so that
  enable must be high in addition to the SRAM being selected, for it to
  be enabled.
- Delete an unused TCM class.

Change-Id: I0b4cc2f76b9ad25222257c6d1ee7e11a806874d4

hdl/chisel/src/kelvin/SramNx128.scala

diff --git a/hdl/chisel/src/kelvin/SramNx128.scala b/hdl/chisel/src/kelvin/SramNx128.scala
index fd68187..2a21a22 100644
--- a/hdl/chisel/src/kelvin/SramNx128.scala
+++ b/hdl/chisel/src/kelvin/SramNx128.scala
@@ -43,7 +43,7 @@
   for (i <- 0 until nSramModules) {
     sramModules(i).io.clock := clock
     sramModules(i).io.addr := io.addr(6, 0)
-    sramModules(i).io.enable := (selectedSram === i.U)
+    sramModules(i).io.enable := (selectedSram === i.U) && io.enable
     sramModules(i).io.write := io.write
     sramModules(i).io.wdata := io.wdata
     sramModules(i).io.wmask := io.wmask

hdl/chisel/src/kelvin/TCM.scala

diff --git a/hdl/chisel/src/kelvin/TCM.scala b/hdl/chisel/src/kelvin/TCM.scala
index 306202a..5900c93 100644
--- a/hdl/chisel/src/kelvin/TCM.scala
+++ b/hdl/chisel/src/kelvin/TCM.scala
@@ -40,61 +40,3 @@
   sram.io.wmask := Cat(io.wmask)
   io.rdata := UIntToVec(sram.io.rdata, tcmSubEntryWidth)
 }
-
-class TCM(p: Parameters, tcmSizeBytes: Int, tcmSubEntryWidth: Int) extends Module {
-  val tcmWidth = p.axi2DataBits
-  val tcmEntries = tcmSizeBytes / (tcmWidth / 8)
-  val tcmSubEntries = tcmWidth / tcmSubEntryWidth
-
-  val io = IO(new Bundle {
-    val addr = Input(UInt(log2Ceil(tcmEntries).W))
-    val enable = Input(Bool())
-    val write = Input(Bool())
-    val wdata = Input(Vec(tcmSubEntries, UInt(tcmSubEntryWidth.W)))
-    val wmask = Input(Vec(tcmSubEntries, Bool()))
-    val rdata = Output(Vec(tcmSubEntries, UInt(tcmSubEntryWidth.W)))
-  })
-
-  val wdataAsUint = Cat(io.wdata)
-  val wmaskAsUint = Cat(io.wmask)
-
-  val memoryRows = 128
-  val memoryWidth = 128
-  val memoryModulesRequired = (tcmSizeBytes * 8 /(memoryWidth * memoryRows))
-  val selectSramBits = log2Ceil(memoryModulesRequired)
-  val selectSramModule = io.addr(io.addr.getWidth - 1, io.addr.getWidth-selectSramBits)
-  val selectSramModuleRead = RegNext(selectSramModule)
-  val addrInternal = io.addr(io.addr.getWidth - 1 - selectSramBits, 0)
-
-  val tcmSrams = (0 until memoryModulesRequired).map(x =>
-      Module(new Sram_12ffcp_128x128))
-
-  // Tie-offs (tie unselected memory inputs to 0)
-  val tcmSramAddrTie = 0.U.asTypeOf(tcmSrams(0).io.addr)
-  val tcmSramEnableTie = 0.U.asTypeOf(tcmSrams(0).io.enable)
-  val tcmSramWriteTie = 0.U.asTypeOf(tcmSrams(0).io.write)
-  val tcmSramWdataTie = 0.U.asTypeOf(tcmSrams(0).io.wdata)
-  val tcmSramWmaskTie = 0.U.asTypeOf(tcmSrams(0).io.wmask)
-
-  for (i <- 0 until memoryModulesRequired) {
-    when (selectSramModule === i.U) {
-      tcmSrams(i).io.addr := io.addr
-      tcmSrams(i).io.enable := io.enable
-      tcmSrams(i).io.write := io.write
-      tcmSrams(i).io.wdata := wdataAsUint
-      tcmSrams(i).io.wmask := wmaskAsUint
-    } .otherwise {
-      tcmSrams(i).io.addr := tcmSramAddrTie
-      tcmSrams(i).io.enable := tcmSramEnableTie
-      tcmSrams(i).io.write := tcmSramWriteTie
-      tcmSrams(i).io.wdata := tcmSramWdataTie
-      tcmSrams(i).io.wmask := wmaskAsUint
-    }
-    tcmSrams(i).io.clock := clock
-  }
-
-  val rdataSelectedUint = VecInit(tcmSrams.map(_.io.rdata))(selectSramModuleRead)
-  val rdataSelected = UIntToVec(rdataSelectedUint, tcmSubEntryWidth)
-
-  io.rdata := rdataSelected
-}