| commit | b437667a95ac388b720d79bd8b3fb7ed3fe9a6b3 | [log] [tgz] |
|---|---|---|
| author | Zhidong.Liang <Zhidong.Liang@verisilicon.com> | Wed Feb 05 16:27:58 2025 +0800 |
| committer | Derek Chow <derekjchow@google.com> | Thu Mar 06 14:56:41 2025 -0800 |
| tree | d0545b5ae00dddd89cabf8932a5d84f4abef5bfe | |
| parent | d7216680d02b19dce81534259f8f59aa2964c3ec [diff] |
remove duplicate definition. Change-Id: I69f1550da7fbdd9dd358b7ea2782ca7f3f69fca5
Kelvin is a RISC-V32IM core with a custom instruction set.
More information on the design can be found in the overview.
Kelvin uses bazel as it's build system. The Verilated simulator for Kelvin can be generated using:
bazel build //tests/verilator_sim:core_sim
The verilog source for the Kelvin core can be generated using:
bazel build //hdl/chisel/src/kelvin:core_cc_library_emit_verilog
Verilog source for the Matcha SoC can be generated using:
bazel clean --expunge # To generate the ToT sha bazel build //hdl/chisel:matcha_kelvin_verilog