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opensecura / hw / kelvin / acf084c3cbd073e0dc15b891029cdfa2fb761f35
commitacf084c3cbd073e0dc15b891029cdfa2fb761f35[log] [tgz]
authortianyu.li <tianyu.li@verisilicon.com>Tue Sep 16 17:34:44 2025 -0700
committerDavid Gao <davidgao@google.com>Wed Sep 17 13:34:38 2025 -0700
treefcb767e6befe9c755a57e2494033941018e2a5b1
parent19eeec6dc2f1f82d98fcfc1612bdd9b99babaa93 [diff]
Adjust vector register order in Decoder for segment load/store. Update rvv_backend_tb for lsu changes.

Change-Id: I60d55196d033b70f5e64baddf17ae2d40e96c574
8 files changed
tree: fcb767e6befe9c755a57e2494033941018e2a5b1
  1. doc/
  2. examples/
  3. external/
  4. fpga/
  5. hdl/
  6. hw_sim/
  7. kelvin_test_utils/
  8. lib/
  9. platforms/
  10. rules/
  11. tests/
  12. third_party/
  13. toolchain/
  14. utils/
  15. .bazelrc
  16. .bazelversion
  17. .gitignore
  18. CONTRIBUTING.md
  19. LICENSE
  20. PREUPLOAD.cfg
  21. README.md
  22. WORKSPACE
README.md

Kelvin

Kelvin is a RISC-V32IM core with a custom instruction set.

Kelvin block diagram

More information on the design can be found in the overview.

Getting Started

  • If you are hardware engineer looking to integrate Kelvin into your design, check out our integration guide.
  • If you are a software engineer looking to write code for Kelvin, start with this tutorial.

Building

Kelvin uses bazel as it's build system. The Verilated simulator for Kelvin can be generated using:

bazel build //tests/verilator_sim:core_sim

The verilog source for the Kelvin core can be generated using:

bazel build //hdl/chisel/src/kelvin:core_cc_library_emit_verilog

Verilog source for the Matcha SoC can be generated using:

bazel clean --expunge  # To generate the ToT sha
bazel build //hdl/chisel:matcha_kelvin_verilog