commit | ab6d5dfc97f687affb80f8d0c05fcf7a08576d0b | [log] [tgz] |
---|---|---|
author | Naveen Dodda <ndodda@google.com> | Tue Jul 22 22:54:58 2025 +0000 |
committer | Naveen Dodda <ndodda@google.com> | Mon Jul 28 20:16:56 2025 +0000 |
tree | da4977537038a7e8e004f97dd7adb653c64965c7 | |
parent | 72f32eb03ba41751903b5e8de3d445a67294b1d4 [diff] |
Widen math ops rvv intrinsics test. NOTE: This test uses a workaround to bipass LSU multi store issue Change-Id: I64898817971275e708122ac9a8beb45f5e0144c2
Kelvin is a RISC-V32IM core with a custom instruction set.
More information on the design can be found in the overview.
Kelvin uses bazel as it's build system. The Verilated simulator for Kelvin can be generated using:
bazel build //tests/verilator_sim:core_sim
The verilog source for the Kelvin core can be generated using:
bazel build //hdl/chisel/src/kelvin:core_cc_library_emit_verilog
Verilog source for the Matcha SoC can be generated using:
bazel clean --expunge # To generate the ToT sha bazel build //hdl/chisel:matcha_kelvin_verilog