commit a08fce5dc737c583de934cf82e768294104edce3
author Yenkai Wang <ykwang@google.com> Fri Jan 17 17:05:06 2025 -0600
committer Yenkai Wang <ykwang@google.com> Fri Jan 17 17:05:06 2025 -0600
tree 17d832831edc9d927b5c1cb7c4d6c06f59f90433
parent 93963ad2ad4becbae3f425181aceb816b546eca6

Emit verilog files for alu, mlu and dvu modules

Change-Id: Icb7080851861f5524fc2414bbb23bcf6cd7e35b4

hdl/chisel/src/kelvin/BUILD

diff --git a/hdl/chisel/src/kelvin/BUILD b/hdl/chisel/src/kelvin/BUILD
index f46b820..d318fdc 100644
--- a/hdl/chisel/src/kelvin/BUILD
+++ b/hdl/chisel/src/kelvin/BUILD
@@ -12,6 +12,7 @@
 # See the License for the specific language governing permissions and
 # limitations under the License.
 
+load("@kelvin_hw//rules:autogen.bzl", "autogen_scm_info")
 load(
     "@kelvin_hw//rules:chisel.bzl",
     "chisel_binary",
@@ -20,7 +21,6 @@
     "chisel_test",
 )
 load("@kelvin_hw//rules:verilog.bzl", "verilog_zip_bundle")
-load("@kelvin_hw//rules:autogen.bzl", "autogen_scm_info")
 
 package(default_visibility = ["//visibility:public"])
 
@@ -68,29 +68,29 @@
     srcs = [
         "rvv/RvvDecodeTest.scala",
     ],
+    args = [
+        "-P",  # Allows parallel tests.
+    ],
     deps = [
         ":kelvin_rvv",
         "//hdl/chisel/src/common:testing",
     ],
-    args = [
-        "-P",  # Allows parallel tests.
-    ],
 )
 
 chisel_test(
     name = "kelvin_scalar_tests",
     srcs = [
+        "scalar/AluTest.scala",
         "scalar/MluTest.scala",
-        "scalar/AluTest.scala"
+    ],
+    args = [
+        "-P",  # Allows parallel tests.
     ],
     deps = [
         ":kelvin_base",
         ":kelvin_scalar",
         "//hdl/chisel/src/common:testing",
     ],
-    args = [
-        "-P",  # Allows parallel tests.
-    ],
 )
 
 chisel_test(
@@ -125,10 +125,10 @@
     srcs = [
         "ClockGate.scala",
     ],
+    resource_strip_prefix = "hdl/verilog",
     resources = [
         "//hdl/verilog:ClockGate.sv",
     ],
-    resource_strip_prefix = "hdl/verilog",
 )
 
 chisel_test(
@@ -136,11 +136,11 @@
     srcs = [
         "ClockGateTest.scala",
     ],
-    deps = [
-        ":kelvin_base",
-        ":clock_gate",
-    ],
     tags = ["verilator"],
+    deps = [
+        ":clock_gate",
+        ":kelvin_base",
+    ],
 )
 
 chisel_library(
@@ -148,10 +148,10 @@
     srcs = [
         "RstSync.scala",
     ],
+    resource_strip_prefix = "hdl/verilog",
     resources = [
         "//hdl/verilog:RstSync.sv",
     ],
-    resource_strip_prefix = "hdl/verilog",
 )
 
 autogen_scm_info(name = "KelvinScmInfo")
@@ -221,8 +221,8 @@
         "scalar/UncachedFetch.scala",
     ],
     deps = [
-        ":kelvin_base",
         ":KelvinScmInfo",
+        ":kelvin_base",
         "//hdl/chisel/src/common",
         "//hdl/chisel/src/common:instruction_buffer",
     ],
@@ -231,18 +231,18 @@
 chisel_library(
     name = "srams",
     srcs = [
-        "Sram_12ffcp_128x128.scala",
-        "Sram_12ffcp_512x128.scala",
-        "Sram_12ffcp_2048x128.scala",
         "SramNx128.scala",
-    ],
-    deps = [
-        ":kelvin_base",
+        "Sram_12ffcp_128x128.scala",
+        "Sram_12ffcp_2048x128.scala",
+        "Sram_12ffcp_512x128.scala",
     ],
     resources = [
         "//hdl/verilog:Sram_12ffcp_128x128.v",
-        "//hdl/verilog:Sram_12ffcp_512x128.v",
         "//hdl/verilog:Sram_12ffcp_2048x128.v",
+        "//hdl/verilog:Sram_12ffcp_512x128.v",
+    ],
+    deps = [
+        ":kelvin_base",
     ],
 )
 
@@ -258,11 +258,11 @@
         "TCM.scala",
     ],
     deps = [
+        ":RstSync",
         ":clock_gate",
         ":kelvin_base",
         ":kelvin_scalar",
         ":kelvin_vector",
-        ":RstSync",
         ":srams",
         "//hdl/chisel/src/bus",
         "//hdl/chisel/src/common",
@@ -280,6 +280,13 @@
 )
 
 chisel_cc_library(
+    name = "alu_cc_library",
+    chisel_lib = ":kelvin_scalar",
+    emit_class = "kelvin.EmitAlu",
+    module_name = "Alu",
+)
+
+chisel_cc_library(
     name = "core_cc_library",
     chisel_lib = ":kelvin",
     emit_class = "kelvin.EmitCore",
@@ -338,11 +345,11 @@
         "--moduleName=CoreMini",
         "--useAxi",
     ],
+    module_name = "CoreMiniAxi",
+    verilog_file_path = "CoreMiniAxi.sv",
     vopts = [
         "-DUSE_GENERIC",
     ],
-    module_name = "CoreMiniAxi",
-    verilog_file_path = "CoreMiniAxi.sv",
 )
 
 verilog_zip_bundle(
@@ -358,6 +365,20 @@
 )
 
 chisel_cc_library(
+    name = "dvu_cc_library",
+    chisel_lib = ":kelvin_scalar",
+    emit_class = "kelvin.EmitDvu",
+    module_name = "Dvu",
+)
+
+chisel_cc_library(
+    name = "mlu_cc_library",
+    chisel_lib = ":kelvin_scalar",
+    emit_class = "kelvin.EmitMlu",
+    module_name = "Mlu",
+)
+
+chisel_cc_library(
     name = "l1dcache_cc_library",
     chisel_lib = ":kelvin",
     emit_class = "kelvin.EmitL1DCache",

hdl/chisel/src/kelvin/scalar/Alu.scala

diff --git a/hdl/chisel/src/kelvin/scalar/Alu.scala b/hdl/chisel/src/kelvin/scalar/Alu.scala
index 3464848..a9009af 100644
--- a/hdl/chisel/src/kelvin/scalar/Alu.scala
+++ b/hdl/chisel/src/kelvin/scalar/Alu.scala
@@ -17,6 +17,7 @@
 import chisel3._
 import chisel3.util._
 import common._
+import _root_.circt.stage.ChiselStage
 
 object Alu {
   def apply(p: Parameters): Alu = {
@@ -133,3 +134,8 @@
   assert(!(valid && !io.rs1.valid && !op.isOneOf(AluOp.LUI)))
   assert(!(valid && !io.rs2.valid && !rs1Only))
 }
+
+object EmitAlu extends App {
+  val p = new Parameters
+  ChiselStage.emitSystemVerilogFile(new Alu(p), args)
+}