| commit | a08fce5dc737c583de934cf82e768294104edce3 | [log] [tgz] |
|---|---|---|
| author | Yenkai Wang <ykwang@google.com> | Fri Jan 17 17:05:06 2025 -0600 |
| committer | Yenkai Wang <ykwang@google.com> | Fri Jan 17 17:05:06 2025 -0600 |
| tree | 17d832831edc9d927b5c1cb7c4d6c06f59f90433 | |
| parent | 93963ad2ad4becbae3f425181aceb816b546eca6 [diff] |
Emit verilog files for alu, mlu and dvu modules Change-Id: Icb7080851861f5524fc2414bbb23bcf6cd7e35b4
Kelvin is a RISC-V32IM core with a custom instruction set.
More information on the design can be found in the overview.
Kelvin uses bazel as it's build system. The Verilated simulator for Kelvin can be generated using:
bazel build //tests/verilator_sim:core_sim
The verilog source for the Kelvin core can be generated using:
bazel build //hdl/chisel/src/kelvin:core_cc_library_emit_verilog
Verilog source for the Matcha SoC can be generated using:
bazel clean --expunge # To generate the ToT sha bazel build //hdl/chisel:matcha_kelvin_verilog