commit 9aebc9044e31738389683697128016e31044fb90
author Pu Wang <pu.wang@verisilicon.com> Mon Dec 30 16:36:41 2024 +0800
committer Derek Chow <derekjchow@google.com> Wed Jan 15 10:06:48 2025 -0800
tree f1e37d95f410a9f851e1ca0d1de25be30b195f03
parent 880e0ff60d0103eeddfc02c28281be0d6f8b8454

update illegal inst check in behavior model.

Change-Id: I53dee2d270f0e7becf0f46549f45c05c880d4b78

hdl/verilog/rvv/sve/rvv_backend_tb/src/rvv_behavior_model.sv

diff --git a/hdl/verilog/rvv/sve/rvv_backend_tb/src/rvv_behavior_model.sv b/hdl/verilog/rvv/sve/rvv_backend_tb/src/rvv_behavior_model.sv
index a7ba345..5406ffa 100644
--- a/hdl/verilog/rvv/sve/rvv_backend_tb/src/rvv_behavior_model.sv
+++ b/hdl/verilog/rvv/sve/rvv_backend_tb/src/rvv_behavior_model.sv
@@ -156,8 +156,7 @@
       @(posedge rvs_if.clk);
       if(rvs_if.rst_n) begin
       rt_event = rvs_if.rt_event;
-      repeat(`NUM_RT_UOP) begin
-      if(rt_event[0]) begin
+      while(rt_event[0]) begin
         // --------------------------------------------------
         // 0. Get inst and update VCSR
         if(inst_queue.size()>0) begin
@@ -374,7 +373,7 @@
               dest_reg_idx, dest_reg_idx+dest_emul, src1_reg_idx, src1_reg_idx+src1_emul));
           continue;
         end
-        if(inst_tr.dest_type == VRF && vm == 0 && dest_eew == 1 /*&& TODO scalar result of a reduction*/ && dest_reg_idx == 0) begin
+        if(inst_tr.dest_type == VRF && vm == 0 && dest_reg_idx == 0 && (dest_eew != EEW1 /*|| TODO scalar result of a reduction*/)) begin
           `uvm_warning("MDL/INST_CHECKER", $sformatf("Ch32.5.3. Dest vrf index(%0d) overlap source mask register v0. Ignored.", dest_reg_idx));
           continue;
         end
@@ -464,8 +463,7 @@
         `uvm_info("DEBUG",inst_tr.sprint(),UVM_HIGH)
         rt_ap.write(inst_tr);
         rt_event = rt_event >> 1;
-      end // if(rt_event[0])
-      end // repeat 
+      end // while(rt_event[0])
       end // rst_n
     end // forever
   endtask

hdl/verilog/rvv/sve/rvv_backend_tb/tests/rvv_backend_test.sv

diff --git a/hdl/verilog/rvv/sve/rvv_backend_tb/tests/rvv_backend_test.sv b/hdl/verilog/rvv/sve/rvv_backend_tb/tests/rvv_backend_test.sv
index 5709757..fec2719 100644
--- a/hdl/verilog/rvv/sve/rvv_backend_tb/tests/rvv_backend_test.sv
+++ b/hdl/verilog/rvv/sve/rvv_backend_tb/tests/rvv_backend_test.sv
@@ -24,7 +24,7 @@
   virtual function void build_phase(uvm_phase phase);
     super.build_phase(phase);
     env = rvv_backend_env::type_id::create("env", this);
-    uvm_top.set_timeout(5000ns,1);
+    uvm_top.set_timeout(100000ns,1);
     if(!uvm_config_db#(v_if1)::get(this, "", "rvs_if", rvs_if)) begin
       `uvm_fatal("TEST/NOVIF", "No virtual interface specified for this agent instance")
     end
@@ -54,6 +54,9 @@
       uvm_config_db#(bit)::set(uvm_root::get(), "*", "all_one_for_agn", 1'b1);
     if($value$plusargs("inst_queue_depth=%d", inst_queue_depth))
       uvm_config_db#(int)::set(uvm_root::get(), "*", "inst_queue_depth", inst_queue_depth);
+    else
+      // give default value
+      uvm_config_db#(int)::set(uvm_root::get(), "*", "inst_queue_depth", inst_queue_depth);
   endfunction
 
   virtual function void connect_phase(uvm_phase phase);