Move several bus defs to a separate location
-Decouples bus definitions that rely only on parameter information from
the entire core library and core instantiations
-chai_sim target is able to build
Change-Id: I4adc88c8ab0507591ea817deae4baa9cbc5b63ba
diff --git a/hdl/chisel/src/kelvin/Axi.scala b/hdl/chisel/src/bus/Axi.scala
similarity index 99%
rename from hdl/chisel/src/kelvin/Axi.scala
rename to hdl/chisel/src/bus/Axi.scala
index 95016f9..2d9b39a 100644
--- a/hdl/chisel/src/kelvin/Axi.scala
+++ b/hdl/chisel/src/bus/Axi.scala
@@ -12,7 +12,7 @@
// See the License for the specific language governing permissions and
// limitations under the License.
-package kelvin
+package bus
import chisel3._
import chisel3.util._
diff --git a/hdl/chisel/src/bus/BUILD b/hdl/chisel/src/bus/BUILD
new file mode 100644
index 0000000..cbc3eff
--- /dev/null
+++ b/hdl/chisel/src/bus/BUILD
@@ -0,0 +1,33 @@
+# Copyright 2024 Google LLC
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+
+load(
+ "@kelvin_hw//rules:chisel.bzl",
+ "chisel_library",
+)
+
+package(default_visibility = ["//visibility:public"])
+
+chisel_library(
+ name = "bus",
+ srcs = [
+ "Axi.scala",
+ "KelvinMemIO.scala",
+ "KelvinToTlul.scala",
+ "TileLinkUL.scala",
+ ],
+ deps = [
+ "//hdl/chisel/src/kelvin:kelvin_params",
+ ],
+)
diff --git a/hdl/chisel/src/bus/KelvinMemIO.scala b/hdl/chisel/src/bus/KelvinMemIO.scala
new file mode 100644
index 0000000..71c7de7
--- /dev/null
+++ b/hdl/chisel/src/bus/KelvinMemIO.scala
@@ -0,0 +1,31 @@
+// Copyright 2024 Google LLC
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+// http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+
+package bus
+
+import chisel3._
+import chisel3.util._
+
+class KelvinMemIO(p: kelvin.Parameters) extends Bundle {
+ val cvalid = (Output(Bool()))
+ val cready = (Input(Bool()))
+ val cwrite = (Output(Bool()))
+ val caddr = (Output(UInt(p.axiSysAddrBits.W)))
+ val cid = (Output(UInt(p.axiSysIdBits.W)))
+ val wdata = (Output(UInt(p.axiSysDataBits.W)))
+ val wmask = (Output(UInt((p.axiSysDataBits / 8).W)))
+ val rvalid = (Input(Bool()))
+ val rid = (Input(UInt(p.axiSysIdBits.W)))
+ val rdata = (Input(UInt(p.axiSysDataBits.W)))
+}
diff --git a/hdl/chisel/src/chai/KelvinToTlul.scala b/hdl/chisel/src/bus/KelvinToTlul.scala
similarity index 73%
rename from hdl/chisel/src/chai/KelvinToTlul.scala
rename to hdl/chisel/src/bus/KelvinToTlul.scala
index c8573c2..5ca32a1 100644
--- a/hdl/chisel/src/chai/KelvinToTlul.scala
+++ b/hdl/chisel/src/bus/KelvinToTlul.scala
@@ -12,29 +12,31 @@
// See the License for the specific language governing permissions and
// limitations under the License.
-package chai
+package bus
import chisel3._
import chisel3.util._
+import bus._
+
object KelvinToTlul {
object State extends ChiselEnum {
val sIdle, sWaitForReady, sWaitForResponse = Value
}
- def apply(tlul_p: kelvin.TLULParameters, kelvin_p: kelvin.Parameters): KelvinToTlul = {
+ def apply(tlul_p: TLULParameters, kelvin_p: kelvin.Parameters): KelvinToTlul = {
return Module(new KelvinToTlul(tlul_p, kelvin_p))
}
}
-class KelvinToTlul(tlul_p: kelvin.TLULParameters, kelvin_p: kelvin.Parameters) extends Module {
+class KelvinToTlul(tlul_p: TLULParameters, kelvin_p: kelvin.Parameters) extends Module {
import KelvinToTlul.State
import KelvinToTlul.State._
val io = IO(new Bundle {
- val tl_i = Input(new _root_.kelvin.TileLinkULIO_D2H(tlul_p))
- val tl_o = Output(new _root_.kelvin.TileLinkULIO_H2D(tlul_p))
- val kelvin = Flipped(new matcha.KelvinMemIO(kelvin_p))
+ val tl_i = Input(new TileLinkULIO_D2H(tlul_p))
+ val tl_o = Output(new TileLinkULIO_H2D(tlul_p))
+ val kelvin = Flipped(new KelvinMemIO(kelvin_p))
})
val state = RegInit(sIdle)
@@ -43,7 +45,7 @@
.map(x => Mux(io.kelvin.wmask(x), 0xff.U(wmask_width.W) << (x * 8).U, 0.U(wmask_width.W)))
.reduce(_ | _)
- io.tl_o := 0.U.asTypeOf(new kelvin.TileLinkULIO_H2D(tlul_p))
+ io.tl_o := 0.U.asTypeOf(new TileLinkULIO_H2D(tlul_p))
io.tl_o.a_user.instr_type := 9.U
io.tl_o.a_source := 0.U
io.tl_o.d_ready := true.B
@@ -68,7 +70,7 @@
io.tl_o.a_valid := true.B
io.tl_o.a_address := io.kelvin.caddr
val cwrite = io.kelvin.cwrite
- io.tl_o.a_opcode := Mux(cwrite, kelvin.TLULOpcodesA.PutFullData.asUInt, kelvin.TLULOpcodesA.Get.asUInt)
+ io.tl_o.a_opcode := Mux(cwrite, TLULOpcodesA.PutFullData.asUInt, TLULOpcodesA.Get.asUInt)
io.tl_o.a_data := Mux(cwrite, io.kelvin.wdata & wmask_bits, 0.U)
state := Mux(io.tl_i.a_ready, sWaitForResponse, sWaitForReady)
}
@@ -81,26 +83,26 @@
is(sWaitForResponse) {
io.tl_o.a_valid := false.B
when(io.tl_i.d_valid) {
- val (value, valid) = kelvin.TLULOpcodesD.safe(io.tl_i.d_opcode)
- val valid2 = valid && (value =/= kelvin.TLULOpcodesD.End)
+ val (value, valid) = TLULOpcodesD.safe(io.tl_i.d_opcode)
+ val valid2 = valid && (value =/= TLULOpcodesD.End)
assert(valid2, "Received invalid TLUL-D opcode\n")
val rdata = chisel3.util.MuxLookup(value, 0.U(32.W))(
Array(
- kelvin.TLULOpcodesD.AccessAck -> 0.U,
- kelvin.TLULOpcodesD.AccessAckData -> io.tl_i.d_data
+ TLULOpcodesD.AccessAck -> 0.U,
+ TLULOpcodesD.AccessAckData -> io.tl_i.d_data
)
)
val rvalid = chisel3.util.MuxLookup(value, false.B)(
Array(
- kelvin.TLULOpcodesD.AccessAck -> false.B,
- kelvin.TLULOpcodesD.AccessAckData -> true.B
+ TLULOpcodesD.AccessAck -> false.B,
+ TLULOpcodesD.AccessAckData -> true.B
)
)
val rid = chisel3.util.MuxLookup(value, 0.U)(
Array(
- kelvin.TLULOpcodesD.AccessAck -> 0.U,
- kelvin.TLULOpcodesD.AccessAckData -> io.kelvin.cid
+ TLULOpcodesD.AccessAck -> 0.U,
+ TLULOpcodesD.AccessAckData -> io.kelvin.cid
)
)
io.kelvin.rvalid := rvalid
diff --git a/hdl/chisel/src/kelvin/TileLinkUL.scala b/hdl/chisel/src/bus/TileLinkUL.scala
similarity index 98%
rename from hdl/chisel/src/kelvin/TileLinkUL.scala
rename to hdl/chisel/src/bus/TileLinkUL.scala
index 155fa3d..0be7596 100644
--- a/hdl/chisel/src/kelvin/TileLinkUL.scala
+++ b/hdl/chisel/src/bus/TileLinkUL.scala
@@ -12,10 +12,12 @@
// See the License for the specific language governing permissions and
// limitations under the License.
-package kelvin
+package bus
import chisel3._
import chisel3.util._
+
+import kelvin.MemoryRegion
import _root_.circt.stage.ChiselStage
case class TLULParameters() {
diff --git a/hdl/chisel/src/chai/BUILD b/hdl/chisel/src/chai/BUILD
index b4e1c48..1a1ffb5 100644
--- a/hdl/chisel/src/chai/BUILD
+++ b/hdl/chisel/src/chai/BUILD
@@ -20,13 +20,13 @@
name = "chai",
srcs = [
"ChAI.scala",
- "KelvinToTlul.scala",
"TlulAdapterSram.scala",
"Uart.scala",
],
deps = [
- "//hdl/chisel/src/matcha:matcha",
+ "//hdl/chisel/src/bus:bus",
"//hdl/chisel/src/kelvin:kelvin",
+ "//hdl/chisel/src/matcha:matcha",
],
)
diff --git a/hdl/chisel/src/chai/ChAI.scala b/hdl/chisel/src/chai/ChAI.scala
index cfd1ba6..abd9ee5 100644
--- a/hdl/chisel/src/chai/ChAI.scala
+++ b/hdl/chisel/src/chai/ChAI.scala
@@ -16,6 +16,8 @@
import chisel3._
import chisel3.util._
+
+import bus._
import _root_.circt.stage.ChiselStage
case class Parameters() {
@@ -76,8 +78,8 @@
io.fault := u_kelvin.fault
withClockAndReset(io.clk_i, rst_i) {
- val tlul_p = new kelvin.TLULParameters()
- val kelvin_to_tlul = chai.KelvinToTlul(tlul_p, kelvin_p)
+ val tlul_p = new TLULParameters()
+ val kelvin_to_tlul = KelvinToTlul(tlul_p, kelvin_p)
kelvin_to_tlul.io.kelvin <> u_kelvin.mem
val tlul_sram =
@@ -104,7 +106,7 @@
io.uart_tx := uart.io.cio_tx_o
val crossbar =
- Module(new kelvin.TileLinkUL(tlul_p, kelvin_p.m, /* hosts= */ 1))
+ Module(new TileLinkUL(tlul_p, kelvin_p.m, /* hosts= */ 1))
crossbar.io.hosts_a(0) <> kelvin_to_tlul.io.tl_o
crossbar.io.hosts_d(0) <> kelvin_to_tlul.io.tl_i
crossbar.io.devices_a(0) <> tlul_adapter_sram.io.tl_i
diff --git a/hdl/chisel/src/chai/TlulAdapterSram.scala b/hdl/chisel/src/chai/TlulAdapterSram.scala
index 345db11..3836210 100644
--- a/hdl/chisel/src/chai/TlulAdapterSram.scala
+++ b/hdl/chisel/src/chai/TlulAdapterSram.scala
@@ -17,6 +17,8 @@
import chisel3._
import chisel3.util._
+import bus._
+
package object sram_params {
val SramAw = 17
val SramDw = 256
@@ -27,14 +29,14 @@
}
class TlulAdapterSram extends BlackBox {
- val tlul_p = new kelvin.TLULParameters()
+ val tlul_p = new TLULParameters()
val io = IO(new Bundle {
val clk_i = Input(Clock())
val rst_ni = Input(AsyncReset())
// TL-UL
- val tl_i = Input(new kelvin.TileLinkULIO_H2D(tlul_p))
- val tl_o = Output(new kelvin.TileLinkULIO_D2H(tlul_p))
+ val tl_i = Input(new TileLinkULIO_H2D(tlul_p))
+ val tl_o = Output(new TileLinkULIO_D2H(tlul_p))
// control
val en_ifetch_i = Input(UInt(4.W)) // mubi4_t
diff --git a/hdl/chisel/src/chai/Uart.scala b/hdl/chisel/src/chai/Uart.scala
index 4fa3090..8003503 100644
--- a/hdl/chisel/src/chai/Uart.scala
+++ b/hdl/chisel/src/chai/Uart.scala
@@ -17,13 +17,15 @@
import chisel3._
import chisel3.util._
-class Uart(tlul_p: kelvin.TLULParameters) extends BlackBox {
+import bus._
+
+class Uart(tlul_p: TLULParameters) extends BlackBox {
val io = IO(new Bundle {
val clk_i = Input(Clock())
val rst_ni = Input(AsyncReset())
- val tl_i = Input(new kelvin.TileLinkULIO_H2D(tlul_p))
- val tl_o = Output(new kelvin.TileLinkULIO_D2H(tlul_p))
+ val tl_i = Input(new TileLinkULIO_H2D(tlul_p))
+ val tl_o = Output(new TileLinkULIO_D2H(tlul_p))
// These have some alert_{rx|tx}_t types.
val alert_rx_i = Input(UInt(4.W))
diff --git a/hdl/chisel/src/kelvin/BUILD b/hdl/chisel/src/kelvin/BUILD
index a1c550e..fd14ade 100644
--- a/hdl/chisel/src/kelvin/BUILD
+++ b/hdl/chisel/src/kelvin/BUILD
@@ -61,7 +61,6 @@
chisel_library(
name = "kelvin",
srcs = [
- "Axi.scala",
"ClockGate.scala",
"Core.scala",
"DBus2Axi.scala",
@@ -70,7 +69,6 @@
"L1ICache.scala",
"Library.scala",
"Parameters.scala",
- "TileLinkUL.scala",
"scalar/Alu.scala",
"scalar/Bru.scala",
"scalar/Csr.scala",
@@ -104,10 +102,20 @@
"vector/VSt.scala",
],
deps = [
+ "//hdl/chisel/src/bus",
"//hdl/chisel/src/common",
],
)
+chisel_library(
+ name = "kelvin_params",
+ srcs = [
+ "Parameters.scala",
+ ],
+ deps = [
+ ],
+)
+
chisel_cc_library(
name = "core_cc_library",
chisel_lib = ":kelvin",
diff --git a/hdl/chisel/src/kelvin/Core.scala b/hdl/chisel/src/kelvin/Core.scala
index 72b1c03..298ee01 100644
--- a/hdl/chisel/src/kelvin/Core.scala
+++ b/hdl/chisel/src/kelvin/Core.scala
@@ -16,6 +16,8 @@
import chisel3._
import chisel3.util._
+
+import bus.AxiMasterIO
import common._
import _root_.circt.stage.ChiselStage
diff --git a/hdl/chisel/src/kelvin/DBus2Axi.scala b/hdl/chisel/src/kelvin/DBus2Axi.scala
index 55ae7db..ebe056a 100644
--- a/hdl/chisel/src/kelvin/DBus2Axi.scala
+++ b/hdl/chisel/src/kelvin/DBus2Axi.scala
@@ -16,6 +16,8 @@
import chisel3._
import chisel3.util._
+
+import bus.AxiMasterIO
import common._
import _root_.circt.stage.ChiselStage
diff --git a/hdl/chisel/src/kelvin/L1DCache.scala b/hdl/chisel/src/kelvin/L1DCache.scala
index 94d88ae..67b9d48 100644
--- a/hdl/chisel/src/kelvin/L1DCache.scala
+++ b/hdl/chisel/src/kelvin/L1DCache.scala
@@ -17,6 +17,8 @@
import chisel3._
import chisel3.util._
import chisel3.experimental.ChiselEnum
+
+import bus.AxiMasterIO
import common._
import _root_.circt.stage.ChiselStage
diff --git a/hdl/chisel/src/kelvin/L1ICache.scala b/hdl/chisel/src/kelvin/L1ICache.scala
index 90cb912..7f2dedc 100644
--- a/hdl/chisel/src/kelvin/L1ICache.scala
+++ b/hdl/chisel/src/kelvin/L1ICache.scala
@@ -16,6 +16,8 @@
import chisel3._
import chisel3.util._
+
+import bus.AxiMasterReadIO
import common._
import _root_.circt.stage.ChiselStage
diff --git a/hdl/chisel/src/kelvin/vector/VCore.scala b/hdl/chisel/src/kelvin/vector/VCore.scala
index d9cc36e..b1252e7 100644
--- a/hdl/chisel/src/kelvin/vector/VCore.scala
+++ b/hdl/chisel/src/kelvin/vector/VCore.scala
@@ -18,6 +18,8 @@
import chisel3._
import chisel3.util._
+
+import bus._
import common._
object VCore {
diff --git a/hdl/chisel/src/kelvin/vector/VLd.scala b/hdl/chisel/src/kelvin/vector/VLd.scala
index bfbda33..0954a05 100644
--- a/hdl/chisel/src/kelvin/vector/VLd.scala
+++ b/hdl/chisel/src/kelvin/vector/VLd.scala
@@ -18,6 +18,8 @@
import chisel3._
import chisel3.util._
+
+import bus.AxiMasterReadIO
import common._
import _root_.circt.stage.ChiselStage
diff --git a/hdl/chisel/src/kelvin/vector/VSt.scala b/hdl/chisel/src/kelvin/vector/VSt.scala
index 638f709..12d459b 100644
--- a/hdl/chisel/src/kelvin/vector/VSt.scala
+++ b/hdl/chisel/src/kelvin/vector/VSt.scala
@@ -18,6 +18,8 @@
import chisel3._
import chisel3.util._
+
+import bus.AxiMasterWriteIO
import common._
import _root_.circt.stage.ChiselStage
diff --git a/hdl/chisel/src/matcha/Axi2Sram.scala b/hdl/chisel/src/matcha/Axi2Sram.scala
index 38914d5..220c49a 100644
--- a/hdl/chisel/src/matcha/Axi2Sram.scala
+++ b/hdl/chisel/src/matcha/Axi2Sram.scala
@@ -16,7 +16,10 @@
import chisel3._
import chisel3.util._
+
+import bus._
import common._
+import kelvin._
import _root_.circt.stage.ChiselStage
object Axi2Sram {
@@ -29,14 +32,14 @@
class Axi2Sram(p: kelvin.Parameters) extends Module {
val io = IO(new Bundle {
// Vector TCM
- val in0 = Flipped(new kelvin.AxiMasterIO(p.axiSysAddrBits, p.axiSysDataBits, p.axiSysIdBits))
+ val in0 = Flipped(new AxiMasterIO(p.axiSysAddrBits, p.axiSysDataBits, p.axiSysIdBits))
// Scalar DBus
- val in1 = Flipped(new kelvin.AxiMasterIO(p.axiSysAddrBits, p.axiSysDataBits, p.axiSysIdBits))
+ val in1 = Flipped(new AxiMasterIO(p.axiSysAddrBits, p.axiSysDataBits, p.axiSysIdBits))
// L1DCache
- val in2 = Flipped(new kelvin.AxiMasterIO(p.axiSysAddrBits, p.axiSysDataBits, p.axiSysIdBits))
+ val in2 = Flipped(new AxiMasterIO(p.axiSysAddrBits, p.axiSysDataBits, p.axiSysIdBits))
// L1ICache
val in3 = new Bundle {
- val read = Flipped(new kelvin.AxiMasterReadIO(p.axiSysAddrBits, p.axiSysDataBits, p.axiSysIdBits))
+ val read = Flipped(new AxiMasterReadIO(p.axiSysAddrBits, p.axiSysDataBits, p.axiSysIdBits))
}
// SRAM port
val out = new CrossbarIO(p.axiSysAddrBits, p.axiSysDataBits, p.axiSysIdBits)
diff --git a/hdl/chisel/src/matcha/BUILD b/hdl/chisel/src/matcha/BUILD
index ebbc792..16caad5 100644
--- a/hdl/chisel/src/matcha/BUILD
+++ b/hdl/chisel/src/matcha/BUILD
@@ -25,6 +25,7 @@
"MatchaParameters.scala",
],
deps = [
+ "//hdl/chisel/src/bus:bus",
"//hdl/chisel/src/common:common",
"//hdl/chisel/src/kelvin:kelvin",
],
diff --git a/hdl/chisel/src/matcha/Kelvin.scala b/hdl/chisel/src/matcha/Kelvin.scala
index ad5a386..4c781d7 100644
--- a/hdl/chisel/src/matcha/Kelvin.scala
+++ b/hdl/chisel/src/matcha/Kelvin.scala
@@ -16,22 +16,11 @@
import chisel3._
import chisel3.util._
+
+import bus.KelvinMemIO
import common._
import _root_.circt.stage.ChiselStage
-class KelvinMemIO(p: kelvin.Parameters) extends Bundle {
- val cvalid = (Output(Bool()))
- val cready = (Input(Bool()))
- val cwrite = (Output(Bool()))
- val caddr = (Output(UInt(p.axiSysAddrBits.W)))
- val cid = (Output(UInt(p.axiSysIdBits.W)))
- val wdata = (Output(UInt(p.axiSysDataBits.W)))
- val wmask = (Output(UInt((p.axiSysDataBits / 8).W)))
- val rvalid = (Input(Bool()))
- val rid = (Input(UInt(p.axiSysIdBits.W)))
- val rdata = (Input(UInt(p.axiSysDataBits.W)))
-}
-
object Kelvin {
def apply(p: kelvin.Parameters): Kelvin = {
return Module(new Kelvin(p))
@@ -105,7 +94,7 @@
slog := core.io.slog
// -------------------------------------------------------------------------
- // Debug Request.
+ // Debug Interface.
core.io.debug_req := debug_req
// -------------------------------------------------------------------------
