commit	976ad5dcee4754ef98ef407fabbdd51ed7045c8d	[log] [tgz]
author	Michael Hoang <hoangm@google.com>	Mon Mar 11 20:15:04 2024 +0000
committer	Michael Hoang <hoangm@google.com>	Tue Mar 12 14:57:11 2024 +0000
tree	6c4992ca8d4a4c769a653c925f3facfaaa2e99e6
parent	8224aa2f71f97f218b8fe403d929264e2fd5b2f0 [diff]

Move several bus defs to a separate location

-Decouples bus definitions that rely only on parameter information from
the entire core library and core instantiations
-chai_sim target is able to build

Change-Id: I4adc88c8ab0507591ea817deae4baa9cbc5b63ba

hdl/chisel/src/bus/Axi.scala[Renamed from hdl/chisel/src/kelvin/Axi.scala - diff]
hdl/chisel/src/bus/BUILD[Added - diff]
hdl/chisel/src/bus/KelvinMemIO.scala[Added - diff]
hdl/chisel/src/bus/KelvinToTlul.scala[Renamed from hdl/chisel/src/chai/KelvinToTlul.scala - diff]
hdl/chisel/src/bus/TileLinkUL.scala[Renamed from hdl/chisel/src/kelvin/TileLinkUL.scala - diff]
hdl/chisel/src/chai/BUILD[diff]
hdl/chisel/src/chai/ChAI.scala[diff]
hdl/chisel/src/chai/TlulAdapterSram.scala[diff]
hdl/chisel/src/chai/Uart.scala[diff]
hdl/chisel/src/kelvin/BUILD[diff]
hdl/chisel/src/kelvin/Core.scala[diff]
hdl/chisel/src/kelvin/DBus2Axi.scala[diff]
hdl/chisel/src/kelvin/L1DCache.scala[diff]
hdl/chisel/src/kelvin/L1ICache.scala[diff]
hdl/chisel/src/kelvin/vector/VCore.scala[diff]
hdl/chisel/src/kelvin/vector/VLd.scala[diff]
hdl/chisel/src/kelvin/vector/VSt.scala[diff]
hdl/chisel/src/matcha/Axi2Sram.scala[diff]
hdl/chisel/src/matcha/BUILD[diff]
hdl/chisel/src/matcha/Kelvin.scala[diff]

20 files changed

tree: 6c4992ca8d4a4c769a653c925f3facfaaa2e99e6

README.md

Kelvin

Kelvin is a RISC-V32IM core with a custom instruction set.

Kelvin block diagram

More information on the design can be found in the overview.

Building

Kelvin uses bazel as it's build system. The Verilated simulator for Kelvin can be generated using:

bazel build //tests/verilator_sim:core_sim

The verilog source for the Kelvin core can be generated using:

bazel build //hdl/chisel:core_cc_library_emit_verilog

Verilog source for the Matcha SoC can be generated using:

bazel clean --expunge  # To generate the ToT sha
bazel build //hdl/chisel:matcha_kelvin_verilog