| commit | 919dfb5ef9dad644a23a2904ce55174219522fd4 | [log] [tgz] |
|---|---|---|
| author | Derek Chow <derekjchow@google.com> | Wed Oct 02 13:33:04 2024 -0700 |
| committer | Derek Chow <derekjchow@google.com> | Tue Nov 26 01:49:33 2024 +0000 |
| tree | 5b99383ae49d4a4522faac791631a888a82d9366 | |
| parent | e6ef87b710ad8fae6aa433bfd6bcd55131d3c938 [diff] |
Add MultiFifo MultiFifo is a Fifo implementation that can enqueue/dequeue multiple elements in a cycle. Change-Id: I36087f2a3bb5f4e7517eb59ce3a429f6201e9fd7
Kelvin is a RISC-V32IM core with a custom instruction set.
More information on the design can be found in the overview.
Kelvin uses bazel as it's build system. The Verilated simulator for Kelvin can be generated using:
bazel build //tests/verilator_sim:core_sim
The verilog source for the Kelvin core can be generated using:
bazel build //hdl/chisel/src/kelvin:core_cc_library_emit_verilog
Verilog source for the Matcha SoC can be generated using:
bazel clean --expunge # To generate the ToT sha bazel build //hdl/chisel:matcha_kelvin_verilog