Update rvv_backend exclusion file
Change-Id: I6aacbe3c238ec8d4c3f36fd6172a2851524b917b
diff --git a/hdl/verilog/rvv/sve/rvv_backend_tb/coverage/rvv_backend_i3rp6/exfile_mulmac_retire.el b/hdl/verilog/rvv/sve/rvv_backend_tb/coverage/rvv_backend_i3rp6/exfile_mulmac_retire.el
index 0c0fe14..a57e9b7 100644
--- a/hdl/verilog/rvv/sve/rvv_backend_tb/coverage/rvv_backend_i3rp6/exfile_mulmac_retire.el
+++ b/hdl/verilog/rvv/sve/rvv_backend_tb/coverage/rvv_backend_i3rp6/exfile_mulmac_retire.el
@@ -331,3 +331,10 @@
Toggle rob2rt_write_data[2].vector_csr.sew [2] "logic rob2rt_write_data[2].vector_csr.sew[2:0]"
ANNOTATION: "sew[2]==0 in zve32x"
Toggle rob2rt_write_data[1].vector_csr.sew [2] "logic rob2rt_write_data[1].vector_csr.sew[2:0]"
+
+CHECKSUM: "422098002 429448440"
+INSTANCE: rvv_backend_top.DUT.u_mulmac
+ANNOTATION: "mac2rs_uop_ready is always 1"
+Condition 8 "2850154482" "(mac2rob_uop_valid[0] && mac2rs_uop_ready[0]) 1 -1"
+ANNOTATION: "mac2rs_uop_ready is always 1"
+Condition 10 "3420602918" "(mac2rob_uop_valid[1] && mac2rs_uop_ready[1]) 1 -1"
diff --git a/hdl/verilog/rvv/sve/rvv_backend_tb/coverage/rvv_backend_i3rp6/exfile_pmtrdt.el b/hdl/verilog/rvv/sve/rvv_backend_tb/coverage/rvv_backend_i3rp6/exfile_pmtrdt.el
index dc3e63e..cca56fe 100644
--- a/hdl/verilog/rvv/sve/rvv_backend_tb/coverage/rvv_backend_i3rp6/exfile_pmtrdt.el
+++ b/hdl/verilog/rvv/sve/rvv_backend_tb/coverage/rvv_backend_i3rp6/exfile_pmtrdt.el
@@ -275,3 +275,10 @@
Toggle 0to1 datain[1].vector_csr.sew [2] "logic datain[1].vector_csr.sew[2:0]"
ANNOTATION: "sew[2]==0 in zve32x"
Toggle datain[1].vector_csr.sew [2] "logic datain[1].vector_csr.sew[2:0]"
+
+CHECKSUM: "3345021061 2701748790"
+INSTANCE: rvv_backend_top.DUT.u_pmtrdt.gen_pmtrdt_unit[0].u_pmtrdt_unit0
+ANNOTATION: "cmp_res_en_offset = cmp_res_offset >> 2"
+Toggle cmp_res_en_offset [6] "logic cmp_res_en_offset[6:0]"
+ANNOTATION: "cmp_res_en_offset = cmp_res_offset >> 2"
+Toggle cmp_res_en_offset [5] "logic cmp_res_en_offset[6:0]"
