Add CSR tracing to RVVI
Change-Id: Ifc0239c8ffdb4bb149c30e78555614e4c9ef5ba6
diff --git a/hdl/chisel/src/kelvin/Interfaces.scala b/hdl/chisel/src/kelvin/Interfaces.scala
index 1e0f890..f6c9a09 100644
--- a/hdl/chisel/src/kelvin/Interfaces.scala
+++ b/hdl/chisel/src/kelvin/Interfaces.scala
@@ -285,3 +285,9 @@
val float_rs = Option.when(p.enableFloat)(new FRegfileRead)
val debug_mode = Output(Bool())
}
+
+class CsrTraceIO(p: Parameters) extends Bundle {
+ val valid = Bool()
+ val addr = UInt(12.W)
+ val data = UInt(32.W)
+}
diff --git a/hdl/chisel/src/kelvin/RvviTrace.scala b/hdl/chisel/src/kelvin/RvviTrace.scala
index faf2a9a..fb72ee3 100644
--- a/hdl/chisel/src/kelvin/RvviTrace.scala
+++ b/hdl/chisel/src/kelvin/RvviTrace.scala
@@ -142,6 +142,7 @@
class RvviTrace(p: Parameters) extends Module {
val io = IO(new Bundle {
val rb = Input(new RetirementBufferDebugIO(p))
+ val csr = Input(new CsrTraceIO(p))
})
val x_wdata = Wire(Vec(p.retirementBufferSize, Vec(32, UInt(32.W))))
val x_wb = Wire(Vec(p.retirementBufferSize, Vec(32, Bool())))
@@ -207,12 +208,10 @@
v_wb(i)(j) := false.B
}
- ///////////////////////////////////
- // TODO(atv): This is just generally not tracked.
- ///////////////////////////////////
for (j <- 0 until 4096) {
- csr(i)(j) := 0.U.asTypeOf(csr(i)(j))
- csr_wb(i)(j) := false.B
+ val csr_wb_valid = valid && io.csr.valid && (io.csr.addr === j.U)
+ csr(i)(j) := MuxOR(csr_wb_valid, io.csr.data)
+ csr_wb(i)(j) := csr_wb_valid
}
}
-}
\ No newline at end of file
+}
diff --git a/hdl/chisel/src/kelvin/scalar/Csr.scala b/hdl/chisel/src/kelvin/scalar/Csr.scala
index e8c4040..2b92bfd 100644
--- a/hdl/chisel/src/kelvin/scalar/Csr.scala
+++ b/hdl/chisel/src/kelvin/scalar/Csr.scala
@@ -203,6 +203,7 @@
val dcsr_step = Output(Bool())
val next_pc = Input(UInt(32.W))
})
+ val trace = Option.when(p.useRetirementBuffer)(Output(new CsrTraceIO(p)))
})
def LegalizeTdata1(wdata: UInt): Tdata1 = {
@@ -577,6 +578,12 @@
io.rd.bits.addr := req.bits.addr
io.rd.bits.data := rdata
+ if (p.useRetirementBuffer) {
+ io.trace.get.valid := req.valid
+ io.trace.get.addr := req.bits.index
+ io.trace.get.data := wdata
+ }
+
// Assertions.
assert(!(req.valid && !io.rs1.valid))
}
diff --git a/hdl/chisel/src/kelvin/scalar/SCore.scala b/hdl/chisel/src/kelvin/scalar/SCore.scala
index 23a2048..68bfdd3 100644
--- a/hdl/chisel/src/kelvin/scalar/SCore.scala
+++ b/hdl/chisel/src/kelvin/scalar/SCore.scala
@@ -531,6 +531,7 @@
io.debug.rb.get := retirement_buffer.get.io.debug
val rvvi = Module(new RvviTrace(p))
rvvi.io.rb := retirement_buffer.get.io.debug
+ rvvi.io.csr := csr.io.trace.get
}
}
