commit | 8cd3a3a8969adbcce9efad0ced2d3b51b9588b1f | [log] [tgz] |
---|---|---|
author | Alex Van Damme <atv@google.com> | Wed Jul 09 15:09:50 2025 -0700 |
committer | Alex Van Damme <atv@google.com> | Mon Jul 28 13:51:47 2025 -0700 |
tree | 233c91dde6d70184cc53c713cf6c773414bc2cc1 | |
parent | ab6d5dfc97f687affb80f8d0c05fcf7a08576d0b [diff] |
Add CSR tracing to RVVI Change-Id: Ifc0239c8ffdb4bb149c30e78555614e4c9ef5ba6
Kelvin is a RISC-V32IM core with a custom instruction set.
More information on the design can be found in the overview.
Kelvin uses bazel as it's build system. The Verilated simulator for Kelvin can be generated using:
bazel build //tests/verilator_sim:core_sim
The verilog source for the Kelvin core can be generated using:
bazel build //hdl/chisel/src/kelvin:core_cc_library_emit_verilog
Verilog source for the Matcha SoC can be generated using:
bazel clean --expunge # To generate the ToT sha bazel build //hdl/chisel:matcha_kelvin_verilog