fusesoc files for Crossbar
- Add a fusesoc core and build rules to allow exporting Crossbar through
the build system.
Change-Id: Ie754a62333d6762dfb26e22137b6c8c93f0124fc
diff --git a/hdl/chisel/BUILD b/hdl/chisel/BUILD
index c466618..88cf0d0 100644
--- a/hdl/chisel/BUILD
+++ b/hdl/chisel/BUILD
@@ -16,12 +16,14 @@
name = "matcha_kelvin_verilog",
srcs = [
"//hdl/chisel/src/matcha:Kelvin.sv",
+ "//hdl/chisel/src/matcha:Crossbar.sv",
"//hdl/verilog:ClockGate.v",
"//hdl/verilog:Sram_1rw_256x256.v",
"//hdl/verilog:Sram_1rwm_256x288.v",
],
outs = [
"kelvin.sv",
+ "crossbar.sv",
"ClockGate.v",
"Sram_1rw_256x256.v",
"Sram_1rwm_256x288.v",
@@ -34,6 +36,11 @@
\\`define ASSERT_VERBOSE_COND 0
" > $(location kelvin.sv)
cat $(location //hdl/chisel/src/matcha:Kelvin.sv) >> $(location kelvin.sv)
+ echo "\\`define STOP_COND 0
+\\`define PRINTF_COND 0
+\\`define ASSERT_VERBOSE_COND 0
+" > $(location crossbar.sv)
+ cat $(location //hdl/chisel/src/matcha:Crossbar.sv) >> $(location crossbar.sv)
cp -f $(location //hdl/verilog:ClockGate.v) $(location ClockGate.v)
cp -f $(location //hdl/verilog:Sram_1rw_256x256.v) $(location Sram_1rw_256x256.v)
cp -f $(location //hdl/verilog:Sram_1rwm_256x288.v) $(location Sram_1rwm_256x288.v)
@@ -46,10 +53,17 @@
genrule(
name = "kelvin_core",
srcs = [
+ "crossbar.core.in",
"kelvin.core.in",
"matcha_kelvin_verilog",
],
- outs = ["kelvin.core"],
- cmd = "cp -f $(location kelvin.core.in) $@",
+ outs = [
+ "crossbar.core",
+ "kelvin.core",
+ ],
+ cmd = """
+ cp -f $(location kelvin.core.in) $(location kelvin.core)
+ cp -f $(location crossbar.core.in) $(location crossbar.core)
+ """,
visibility = ["//visibility:public"],
)
diff --git a/hdl/chisel/crossbar.core.in b/hdl/chisel/crossbar.core.in
new file mode 100644
index 0000000..730e9d6
--- /dev/null
+++ b/hdl/chisel/crossbar.core.in
@@ -0,0 +1,34 @@
+CAPI=2:
+# Copyright 2023 Google LLC
+# Licensed under the Apache License, Version 2.0, see LICENSE for details.
+# SPDX-License-Identifier: Apache-2.0
+name: "google:ip:crossbar:0.1"
+description: "Kelvin SRAM Crossbar"
+filesets:
+ files_rtl:
+ files:
+ - crossbar.sv
+ file_type: systemVerilogSource
+
+parameters:
+ SYNTHESIS:
+ datatype: bool
+ paramtype: vlogdefine
+
+
+targets:
+ default: &default_target
+ filesets:
+ - files_rtl
+ toplevel: crossbar
+
+ lint:
+ <<: *default_target
+ default_tool: verilator
+ parameters:
+ - SYNTHESIS=true
+ tools:
+ verilator:
+ mode: lint-only
+ verilator_options:
+ - "-Wall"
diff --git a/hdl/chisel/src/matcha/BUILD b/hdl/chisel/src/matcha/BUILD
index 6b10e4e..eb4ab1b 100644
--- a/hdl/chisel/src/matcha/BUILD
+++ b/hdl/chisel/src/matcha/BUILD
@@ -39,4 +39,11 @@
"//hdl/verilog:sram_1rw_256x256",
"//hdl/verilog:sram_1rw_256x288",
],
-)
\ No newline at end of file
+)
+
+chisel_cc_library(
+ name = "crossbar_cc_library",
+ chisel_lib = ":matcha",
+ emit_class = "matcha.EmitCrossbar",
+ module_name = "Crossbar",
+)
