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opensecura / hw / kelvin / 7eb4dec16585041a9e44cef6820d8a8528c34d41
commit7eb4dec16585041a9e44cef6820d8a8528c34d41[log] [tgz]
authorDerek Chow <derekjchow@google.com>Wed Aug 27 20:39:44 2025 -0700
committerDerek Chow <derekjchow@google.com>Tue Sep 02 14:36:18 2025 -0700
tree60891e1113a31c7fe0b194ee3ad6006c63cc9678
parent296d738bd7a11f16664b4f5912a74c527b633b96 [diff]
Add SvGenerationUtils.

Useful functions for interfacing Chisel with SV.

Change-Id: I6f08996d4017f38864eada9a34f6169525a58ecc
3 files changed
tree: 60891e1113a31c7fe0b194ee3ad6006c63cc9678
  1. doc/
  2. examples/
  3. external/
  4. fpga/
  5. hdl/
  6. hw_sim/
  7. kelvin_test_utils/
  8. lib/
  9. platforms/
  10. rules/
  11. tests/
  12. third_party/
  13. toolchain/
  14. utils/
  15. .bazelrc
  16. .bazelversion
  17. .gitignore
  18. CONTRIBUTING.md
  19. LICENSE
  20. PREUPLOAD.cfg
  21. README.md
  22. WORKSPACE
README.md

Kelvin

Kelvin is a RISC-V32IM core with a custom instruction set.

Kelvin block diagram

More information on the design can be found in the overview.

Getting Started

  • If you are hardware engineer looking to integrate Kelvin into your design, check out our integration guide.
  • If you are a software engineer looking to write code for Kelvin, start with this tutorial.

Building

Kelvin uses bazel as it's build system. The Verilated simulator for Kelvin can be generated using:

bazel build //tests/verilator_sim:core_sim

The verilog source for the Kelvin core can be generated using:

bazel build //hdl/chisel/src/kelvin:core_cc_library_emit_verilog

Verilog source for the Matcha SoC can be generated using:

bazel clean --expunge  # To generate the ToT sha
bazel build //hdl/chisel:matcha_kelvin_verilog