commit 785139588bc2b362aa211117c4eea52b02a2ac6a
author Cindy Liu <hcindyl@google.com> Thu Oct 19 14:37:15 2023 -0700
committer Cindy Liu <hcindyl@google.com> Thu Oct 19 14:37:15 2023 -0700
tree 243f390eff7115f462d7402d8c194abaa6545e75
parent 0959e5392846ee5ed9da1705d2a65343c14cdef5

Add l1dcachebank systemc test

Change-Id: I7459fd5dc3645619dfa655956d0d35e448dee55f

tests/verilator_sim/BUILD

diff --git a/tests/verilator_sim/BUILD b/tests/verilator_sim/BUILD
index cd33115..39e150f 100644
--- a/tests/verilator_sim/BUILD
+++ b/tests/verilator_sim/BUILD
@@ -80,6 +80,21 @@
 )
 
 cc_test(
+    name = "l1dcachebank_tb",
+    srcs = [
+        "kelvin/l1dcache_tb.cc",
+    ],
+    defines = [
+        "L1DCACHEBANK",
+    ],
+    deps = [
+        ":kelvin_if",
+        ":sim_libs",
+        "//hdl/chisel:l1dcachebank_cc_library",
+    ],
+)
+
+cc_test(
     name = "l1icache_tb",
     srcs = [
         "kelvin/l1icache_tb.cc",