Google Git
Sign in
opensecura / hw / kelvin / 6178d5da9da877f4565553b9e3b5985e30fde842
commit6178d5da9da877f4565553b9e3b5985e30fde842[log] [tgz]
authorDavid Gao <davidgao@google.com>Tue Sep 16 23:10:57 2025 +0000
committerDavid Gao <davidgao@google.com>Wed Sep 17 13:34:38 2025 -0700
tree260dfd0403f2911d72d5ba4a29f0669b4ff51b30
parentacf084c3cbd073e0dc15b891029cdfa2fb761f35 [diff]
Fix segmented load-store register layout

Order of operations from memory PoV is unchanged.
Order of register access is changed.

The fix is now complete, affected tests are enabled.

Change-Id: Ib7bf17b0d60c18a8b0b4cb8163277cd0afe8e37c
3 files changed
tree: 260dfd0403f2911d72d5ba4a29f0669b4ff51b30
  1. doc/
  2. examples/
  3. external/
  4. fpga/
  5. hdl/
  6. hw_sim/
  7. kelvin_test_utils/
  8. lib/
  9. platforms/
  10. rules/
  11. tests/
  12. third_party/
  13. toolchain/
  14. utils/
  15. .bazelrc
  16. .bazelversion
  17. .gitignore
  18. CONTRIBUTING.md
  19. LICENSE
  20. PREUPLOAD.cfg
  21. README.md
  22. WORKSPACE
README.md

Kelvin

Kelvin is a RISC-V32IM core with a custom instruction set.

Kelvin block diagram

More information on the design can be found in the overview.

Getting Started

  • If you are hardware engineer looking to integrate Kelvin into your design, check out our integration guide.
  • If you are a software engineer looking to write code for Kelvin, start with this tutorial.

Building

Kelvin uses bazel as it's build system. The Verilated simulator for Kelvin can be generated using:

bazel build //tests/verilator_sim:core_sim

The verilog source for the Kelvin core can be generated using:

bazel build //hdl/chisel/src/kelvin:core_cc_library_emit_verilog

Verilog source for the Matcha SoC can be generated using:

bazel clean --expunge  # To generate the ToT sha
bazel build //hdl/chisel:matcha_kelvin_verilog