commit | 94d7eb50d5b422d81c86e89c923edee24399132d | [log] [tgz] |
---|---|---|
author | Derek Chow <derekjchow@google.com> | Mon Jul 21 15:26:43 2025 -0700 |
committer | Derek Chow <derekjchow@google.com> | Sun Jul 27 12:58:17 2025 -0700 |
tree | 58042807533ee00141b4fc45a33622a4a4c87824 | |
parent | ce92821047238a3dbd73a7c54ece84a6f0266959 [diff] |
Respect queue counts in Lsu and Rvv. Use the queue counts from Lsu and Rvv instead of ready/valid to determine if an instruction can be issued. Change-Id: I2f3915f702ab465c641a0930340e56c326905129
Kelvin is a RISC-V32IM core with a custom instruction set.
More information on the design can be found in the overview.
Kelvin uses bazel as it's build system. The Verilated simulator for Kelvin can be generated using:
bazel build //tests/verilator_sim:core_sim
The verilog source for the Kelvin core can be generated using:
bazel build //hdl/chisel/src/kelvin:core_cc_library_emit_verilog
Verilog source for the Matcha SoC can be generated using:
bazel clean --expunge # To generate the ToT sha bazel build //hdl/chisel:matcha_kelvin_verilog