merge derek change in vrf and update tb
Change-Id: If2a1603483047547f1941d5dcdf29025ca48073f
diff --git a/hdl/verilog/rvv/design/rvv_backend_vrf.sv b/hdl/verilog/rvv/design/rvv_backend_vrf.sv
index ba4d6a2..3f99563 100755
--- a/hdl/verilog/rvv/design/rvv_backend_vrf.sv
+++ b/hdl/verilog/rvv/design/rvv_backend_vrf.sv
@@ -42,9 +42,9 @@
logic [`NUM_RT_UOP-1:0][`VLEN-1:0] wr_data;
logic [`NUM_RT_UOP-1:0][`VLENB-1:0] wr_we; // byte enable
logic [`NUM_RT_UOP-1:0][`VLEN-1:0] wr_web; // bit enable
-logic [`NUM_RT_UOP-1:0][`NUM_VRF-1:0][`VLEN-1:0] vrf_wr_wenb;
+logic [`NUM_RT_UOP-1:0][`NUM_VRF-1:0][`VLENB-1:0] vrf_wr_wen;
logic [`NUM_RT_UOP-1:0][`NUM_VRF-1:0][`VLEN-1:0] vrf_wr_data;
-logic [`NUM_VRF-1:0][`VLEN-1:0] vrf_wr_wenb_full;
+logic [`NUM_VRF-1:0][`VLENB-1:0] vrf_wr_wen_full;
logic [`NUM_VRF-1:0][`VLEN-1:0] vrf_wr_data_full;
logic [`NUM_DP_VRF-1:0][`REGFILE_INDEX_WIDTH-1:0] rd_addr;
logic [`NUM_VRF-1:0][`VLEN-1:0] vrf_rd_data_full; // full 32 VLEN data from VRF
@@ -64,11 +64,11 @@
// access VRF. Only write will update input
always_comb begin
- vrf_wr_wenb[j] = 'b0;
+ vrf_wr_wen[j] = 'b0;
vrf_wr_data[j] = 'b0;
if(wr_valid[j]) begin
- vrf_wr_wenb[j][wr_addr[j]] = wr_web[j];
+ vrf_wr_wen[j][wr_addr[j]] = wr_we[j];
vrf_wr_data[j][wr_addr[j]] = wr_data[j]&wr_web[j];
end
end
@@ -77,12 +77,12 @@
// merge all retire data
always_comb begin
- vrf_wr_wenb_full = 'b0;
+ vrf_wr_wen_full = 'b0;
vrf_wr_data_full = 'b0;
for(int i=0; i<`NUM_VRF; i++) begin
for(int h=0; h<`NUM_RT_UOP; h++) begin
- vrf_wr_wenb_full[i] = vrf_wr_wenb_full[i] | vrf_wr_wenb[h][i];
+ vrf_wr_wen_full[i] = vrf_wr_wen_full[i] | vrf_wr_wen[h][i];
vrf_wr_data_full[i] = vrf_wr_data_full[i] | vrf_wr_data[h][i];
end
end
@@ -96,7 +96,7 @@
//Inputs
.clk (clk),
.rst_n (rst_n),
- .wenb (vrf_wr_wenb_full),
+ .wen (vrf_wr_wen_full),
.wdata (vrf_wr_data_full)
);
diff --git a/hdl/verilog/rvv/design/rvv_backend_vrf_reg.sv b/hdl/verilog/rvv/design/rvv_backend_vrf_reg.sv
index 1bcc96d..604fa98 100644
--- a/hdl/verilog/rvv/design/rvv_backend_vrf_reg.sv
+++ b/hdl/verilog/rvv/design/rvv_backend_vrf_reg.sv
@@ -9,12 +9,12 @@
// Outputs
vreg,
// Inputs
- wenb, wdata, clk, rst_n
+ wen, wdata, clk, rst_n
);
output logic [`NUM_VRF-1:0][`VLEN-1:0] vreg;
- input logic [`NUM_VRF-1:0][`VLEN-1:0] wenb; // bit en
+ input logic [`NUM_VRF-1:0][`VLENB-1:0] wen; // byte enable
input logic [`NUM_VRF-1:0][`VLEN-1:0] wdata;
input logic clk;
input logic rst_n;
@@ -23,17 +23,20 @@
genvar i,j;
generate
for (i=0; i<`NUM_VRF; i=i+1) begin
- for (j=0; j<`VLEN; j=j+1) begin
- edff vrf_unit1_reg (
- .q (vreg[i][j]),
- .e (wenb[i][j]),
- .d (wdata[i][j]),
+ for (j=0; j<`VLENB; j=j+1) begin
+ edff #(
+ .T (logic [`BYTE_WIDTH-1:0])
+ )
+ vrf_unit1_reg (
+ .q (vreg[i][j*`BYTE_WIDTH +: `BYTE_WIDTH]),
+ .e (wen[i][j]),
+ .d (wdata[i][j*`BYTE_WIDTH +: `BYTE_WIDTH]),
.clk (clk),
.rst_n (rst_n)
);
`ifdef ASSERT_ON
- `rvv_forbid($isunknown(vreg[i][j]))
- else $error("VREG: data is unknow at vreg[%0d][%0d]",i,j);
+ `rvv_forbid($isunknown(vreg[i][j*`BYTE_WIDTH +: `BYTE_WIDTH]))
+ else $error("VREG: data is unknow at vreg[%0d][%0d:%0d]",i,8*j+7,8*j);
`endif //ASSERT_ON
end //end for loop j
end //end for loop i
diff --git a/hdl/verilog/rvv/sve/rvv_backend_tb/hdl/rvv_backend_top.sv b/hdl/verilog/rvv/sve/rvv_backend_tb/hdl/rvv_backend_top.sv
index e17bbf2..727734d 100644
--- a/hdl/verilog/rvv/sve/rvv_backend_tb/hdl/rvv_backend_top.sv
+++ b/hdl/verilog/rvv/sve/rvv_backend_tb/hdl/rvv_backend_top.sv
@@ -153,7 +153,11 @@
for(int i=0; i<32; i++) begin
vrf_if.vreg[i] = `VRF_PATH.vrf_rd_data_full[i];
end
- vrf_if.vrf_wr_wenb_full = `VRF_PATH.vrf_wr_wenb_full;
+ for(int i=0; i<32; i++) begin
+ for(int j=0; j<`VLENB; j++) begin
+ vrf_if.vrf_wr_wenb_full[i][j*`BYTE_WIDTH +: `BYTE_WIDTH] = {`BYTE_WIDTH{`VRF_PATH.vrf_wr_wen_full[i][j]}};
+ end
+ end
vrf_if.vrf_wr_data_full = `VRF_PATH.vrf_wr_data_full;
vrf_if.vrf_rd_data_full = `VRF_PATH.vrf_rd_data_full;
end: vrf_connect
@@ -216,7 +220,13 @@
assign rvv_intern_if.rob_empty = DUT.u_rob.u_uop_valid_fifo.empty;
/* vrf */
- assign rvv_intern_if.vrf_wr_wenb_full = `VRF_PATH.vrf_wr_wenb_full;
+ always_comb begin
+ for(int i=0; i<32; i++) begin
+ for(int j=0; j<`VLENB; j++) begin
+ rvv_intern_if.vrf_wr_wenb_full[i][j*`BYTE_WIDTH +: `BYTE_WIDTH] = {`BYTE_WIDTH{`VRF_PATH.vrf_wr_wen_full[i][j]}};
+ end
+ end
+ end
// Trap
assign rvv_intern_if.trap_valid_rvs2rvv = DUT.trap_valid_rvs2rvv;
diff --git a/hdl/verilog/rvv/sve/rvv_backend_tb/src/rvs_agent_vrf_interface.sv b/hdl/verilog/rvv/sve/rvv_backend_tb/src/rvs_agent_vrf_interface.sv
index a7715f9..bb153b1 100644
--- a/hdl/verilog/rvv/sve/rvv_backend_tb/src/rvs_agent_vrf_interface.sv
+++ b/hdl/verilog/rvv/sve/rvv_backend_tb/src/rvs_agent_vrf_interface.sv
@@ -15,10 +15,10 @@
logic [`NUM_RT_UOP-1:0] rt_last_uop;
task set_dut_vrf(input int reg_idx, input logic[`VLEN-1:0] value);
- `VRF_PATH.vrf_wr_wenb_full[reg_idx] = '1;
+ `VRF_PATH.vrf_wr_wen_full[reg_idx] = '1;
`VRF_PATH.vrf_wr_data_full[reg_idx] = value;
@(posedge clk);
- `VRF_PATH.vrf_wr_wenb_full[reg_idx] = '0;
+ `VRF_PATH.vrf_wr_wen_full[reg_idx] = '0;
@(posedge clk);
endtask: set_dut_vrf
diff --git a/hdl/verilog/rvv/sve/rvv_backend_tb/tests/rvv_backend_corner_test.sv b/hdl/verilog/rvv/sve/rvv_backend_tb/tests/rvv_backend_corner_test.sv
index 0289e4a..80a2771 100644
--- a/hdl/verilog/rvv/sve/rvv_backend_tb/tests/rvv_backend_corner_test.sv
+++ b/hdl/verilog/rvv/sve/rvv_backend_tb/tests/rvv_backend_corner_test.sv
@@ -1065,4 +1065,66 @@
super.final_phase(phase);
endfunction
endclass: small_evl_test
+
+
+//-----------------------------------------------------------
+// rob_entry_trap_test
+//-----------------------------------------------------------
+class rob_entry_trap_test extends rvv_backend_test;
+
+ rvs_random_sequence_library rvs_seq_lib;
+ inst_rvv_zve32x_vcpop_m_seq vcpop_m_seq;
+ inst_rvv_zve32x_viota_m_seq viota_m_seq;
+ inst_rvv_zve32x_vmv_x_s_seq vmv_x_s_seq;
+ inst_rvv_zve32x_vadd_vx_seq vadd_vx_seq;
+ inst_rvv_zve32x_vse8_v_seq vse8_v_seq;
+ rvs_last_sequence rvs_last_seq;
+
+ `uvm_component_utils(rob_entry_trap_test)
+
+ function new(string name, uvm_component parent);
+ super.new(name, parent);
+ endfunction
+
+ function void build_phase(uvm_phase phase);
+ super.build_phase(phase);
+ uvm_config_db#(bit)::set(uvm_root::get(), "*", "trap_en", 1'b1);
+ uvm_config_db#(bit)::set(uvm_root::get(), "*", "always_trap", 1'b1);
+ endfunction
+
+ function void connect_phase(uvm_phase phase);
+ super.connect_phase(phase);
+ this.set_report_id_action_hier("MDL", UVM_LOG);
+ endfunction
+
+ task main_phase(uvm_phase phase);
+
+ rvs_seq_lib = rvs_random_sequence_library::type_id::create("rvs_seq_lib");
+ rvs_seq_lib.selection_mode = UVM_SEQ_LIB_RAND;
+ rvs_seq_lib.sequence_count = random_inst_num;
+ rvs_seq_lib.add_typewide_sequence(vcpop_m_seq.get_type());
+ rvs_seq_lib.add_typewide_sequence(vcpop_m_seq.get_type());
+ rvs_seq_lib.add_typewide_sequence(vcpop_m_seq.get_type());
+ rvs_seq_lib.add_typewide_sequence(viota_m_seq.get_type());
+ rvs_seq_lib.add_typewide_sequence(viota_m_seq.get_type());
+ rvs_seq_lib.add_typewide_sequence(viota_m_seq.get_type());
+ rvs_seq_lib.add_typewide_sequence(vmv_x_s_seq.get_type());
+ rvs_seq_lib.add_typewide_sequence(vmv_x_s_seq.get_type());
+ rvs_seq_lib.add_typewide_sequence(vmv_x_s_seq.get_type());
+ rvs_seq_lib.add_typewide_sequence(vadd_vx_seq.get_type());
+ rvs_seq_lib.add_typewide_sequence(vse8_v_seq.get_type());
+ rvs_seq_lib.init_sequence_library();
+
+ rand_vrf();
+
+ rvs_seq_lib.start(env.rvs_agt.rvs_sqr);
+
+ rvs_last_seq = rvs_last_sequence::type_id::create("rvs_last_seq", this);
+ rvs_last_seq.start(env.rvs_agt.rvs_sqr);
+ endtask
+
+ function void final_phase(uvm_phase phase);
+ super.final_phase(phase);
+ endfunction
+endclass: rob_entry_trap_test
`endif // RVV_BACKEND_CORNER_TEST__SV
