commit | 653a90858c3b56db41c6d7f2c652c6b4fcd9584f | [log] [tgz] |
---|---|---|
author | pu.wang <pu.wang@verisilicon.com> | Thu Jul 10 10:51:47 2025 -0700 |
committer | Derek Chow <derekjchow@google.com> | Thu Jul 10 16:19:47 2025 -0700 |
tree | 97335eb863d4233662c13b80e06be2f2fbf8c6ef | |
parent | 5a69943136c65ef7576a24575e0e514cd2130eb3 [diff] |
merge derek change in vrf and update tb Change-Id: If2a1603483047547f1941d5dcdf29025ca48073f
Kelvin is a RISC-V32IM core with a custom instruction set.
More information on the design can be found in the overview.
Kelvin uses bazel as it's build system. The Verilated simulator for Kelvin can be generated using:
bazel build //tests/verilator_sim:core_sim
The verilog source for the Kelvin core can be generated using:
bazel build //hdl/chisel/src/kelvin:core_cc_library_emit_verilog
Verilog source for the Matcha SoC can be generated using:
bazel clean --expunge # To generate the ToT sha bazel build //hdl/chisel:matcha_kelvin_verilog