Add option to generate Kelvin-scalar version of Matcha subsystem.
Change-Id: I1391820c4dc0aac4f92b779ea1fe800b73856dd0
diff --git a/hdl/chisel/src/kelvin/Parameters.scala b/hdl/chisel/src/kelvin/Parameters.scala
index 9e0efc4..841c751 100644
--- a/hdl/chisel/src/kelvin/Parameters.scala
+++ b/hdl/chisel/src/kelvin/Parameters.scala
@@ -57,7 +57,7 @@
val vectorCountBits = log2Ceil(vectorBits / 8) + 1 + 2 // +2 stripmine
// Enable Vector
- val enableVector = true
+ var enableVector = true
val vectorAluCount = 2
val vectorReadPorts = (vectorAluCount * 3) + 1
val vectorWritePorts = 6
diff --git a/hdl/chisel/src/matcha/Axi2Sram.scala b/hdl/chisel/src/matcha/Axi2Sram.scala
index 8799a99..beeaab3 100644
--- a/hdl/chisel/src/matcha/Axi2Sram.scala
+++ b/hdl/chisel/src/matcha/Axi2Sram.scala
@@ -32,7 +32,11 @@
class Axi2Sram(p: kelvin.Parameters) extends Module {
val io = IO(new Bundle {
// Vector TCM
- val in0 = Flipped(new AxiMasterIO(p.axiSysAddrBits, p.axiSysDataBits, p.axiSysIdBits))
+ val in0 = if(p.enableVector) {
+ Some(Flipped(new AxiMasterIO(p.axiSysAddrBits, p.axiSysDataBits, p.axiSysIdBits)))
+ } else {
+ None
+ }
// Scalar DBus
val in1 = Flipped(new AxiMasterIO(p.axiSysAddrBits, p.axiSysDataBits, p.axiSysIdBits))
// L1DCache
@@ -108,10 +112,16 @@
val rdata = UInt(p.axiSysDataBits.W)
}, true)
- val readInterfaces = Seq(
- io.in0.read, io.in1.read, io.in2.read, io.in3.read)
- val writeInterfaces = Seq(
- io.in0.write, io.in1.write, io.in2.write)
+ val readInterfaces = if (p.enableVector) {
+ Seq(io.in0.get.read, io.in1.read, io.in2.read, io.in3.read)
+ } else {
+ Seq(io.in1.read, io.in2.read, io.in3.read)
+ }
+ val writeInterfaces = if (p.enableVector) {
+ Seq(io.in0.get.write, io.in1.write, io.in2.write)
+ } else {
+ Seq(io.in1.write, io.in2.write)
+ }
val readCv = readInterfaces.map(_.addr.valid)
val writeCv = writeInterfaces.map(_.addr.valid)
val readValid = readCv.reduce(_ || _)
diff --git a/hdl/chisel/src/matcha/BUILD b/hdl/chisel/src/matcha/BUILD
index 16caad5..a4dc82b 100644
--- a/hdl/chisel/src/matcha/BUILD
+++ b/hdl/chisel/src/matcha/BUILD
@@ -32,6 +32,23 @@
)
chisel_cc_library(
+ name = "kelvin_scalar_cc_library",
+ chisel_lib = ":matcha",
+ emit_class = "matcha.EmitKelvin",
+ module_name = "Kelvin",
+ verilog_deps = [
+ "//hdl/verilog:clock_gate",
+ "//hdl/verilog:sram_1rw_256x256",
+ "//hdl/verilog:sram_1rw_256x288",
+ ],
+ verilog_file_path = "KelvinScalar.sv",
+ gen_flags = [
+ "--enableVector=False",
+ "--moduleName=KelvinScalar",
+ ],
+)
+
+chisel_cc_library(
name = "kelvin_cc_library",
chisel_lib = ":matcha",
emit_class = "matcha.EmitKelvin",
diff --git a/hdl/chisel/src/matcha/Kelvin.scala b/hdl/chisel/src/matcha/Kelvin.scala
index 4c781d7..02b87c5 100644
--- a/hdl/chisel/src/matcha/Kelvin.scala
+++ b/hdl/chisel/src/matcha/Kelvin.scala
@@ -23,11 +23,13 @@
object Kelvin {
def apply(p: kelvin.Parameters): Kelvin = {
- return Module(new Kelvin(p))
+ return Module(new Kelvin(p, "Kelvin"))
}
}
-class Kelvin(p: kelvin.Parameters) extends RawModule {
+class Kelvin(p: kelvin.Parameters, name: String) extends RawModule {
+ override val desiredName = name
+
// IO ports. (RawModule removes default[clock, reset])
val clk_i = IO(Input(Clock()))
val rst_ni = IO(Input(AsyncReset()))
@@ -110,7 +112,7 @@
// -------------------------------------------------------------------------
// Bus Mux.
if (p.enableVector) {
- bus.io.in0 <> core.io.axi0.get
+ bus.io.in0.get <> core.io.axi0.get
}
bus.io.in1 <> core.io.axi1
bus.io.in2 <> l1d.io.axi
@@ -140,6 +142,18 @@
}
object EmitKelvin extends App {
- val p = new kelvin.MatchaParameters
- ChiselStage.emitSystemVerilogFile(new Kelvin(p), args)
+ var p = new kelvin.MatchaParameters
+ var moduleName = "Kelvin"
+ var chiselArgs = List[String]()
+ for (arg <- args) {
+ if (arg.startsWith("--enableVector")) {
+ p.enableVector = arg.split("=")(1).toBoolean
+ } else if (arg.startsWith("--moduleName")) {
+ moduleName = arg.split("=")(1)
+ } else {
+ chiselArgs = chiselArgs :+ arg
+ }
+ }
+ ChiselStage.emitSystemVerilogFile(
+ new Kelvin(p, moduleName), chiselArgs.toArray)
}
diff --git a/rules/chisel.bzl b/rules/chisel.bzl
index 253b51d..7e21e37 100644
--- a/rules/chisel.bzl
+++ b/rules/chisel.bzl
@@ -90,7 +90,9 @@
chisel_lib,
emit_class,
module_name,
- verilog_deps = []):
+ verilog_deps = [],
+ verilog_file_path = "",
+ gen_flags = []):
gen_binary_name = name + "_emit_verilog_binary"
chisel_binary(
name = gen_binary_name,
@@ -98,11 +100,15 @@
main_class = emit_class,
)
+ if verilog_file_path == "":
+ verilog_file_path = module_name + ".sv"
+
+ gen_flags = " ".join(gen_flags)
native.genrule(
name = name + "_emit_verilog",
srcs = [],
- outs = [module_name + ".sv"],
- cmd = "PATH=$$(dirname $(execpath @kelvin_hw//third_party/llvm-firtool:firtool)):$$PATH ./$(location " + gen_binary_name + ") --target-dir $(RULEDIR)",
+ outs = [verilog_file_path],
+ cmd = "PATH=$$(dirname $(execpath @kelvin_hw//third_party/llvm-firtool:firtool)):$$PATH ./$(location " + gen_binary_name + ") --target-dir $(RULEDIR) " + gen_flags,
tools = [
":{}".format(gen_binary_name),
"@kelvin_hw//third_party/llvm-firtool:firtool",
@@ -111,7 +117,7 @@
verilog_library(
name = name + "_verilog",
- srcs = [module_name + ".sv"],
+ srcs = [verilog_file_path],
deps = verilog_deps,
)
