commit 5ff18fad5d576098a714e7f3dace82ceb7826449
author Yenkai Wang <ykwang@google.com> Wed Dec 04 17:47:31 2024 -0600
committer Yenkai Wang <ykwang@google.com> Wed Dec 04 17:52:31 2024 -0600
tree 950df0c9ea6ac11b48d7363b66a2999466aa40a1
parent ef7ec3f7a90866e1a0a656d464392207222f7378

Fix the latch issue in Slice

Change-Id: Id66ab87a8894cd0833e5e60134af9cae386158cb

hdl/chisel/src/common/Slice.scala

diff --git a/hdl/chisel/src/common/Slice.scala b/hdl/chisel/src/common/Slice.scala
index be09884..a53b4bc 100644
--- a/hdl/chisel/src/common/Slice.scala
+++ b/hdl/chisel/src/common/Slice.scala
@@ -68,11 +68,11 @@
 
     when (ovalid && full) {
       mem(0) := mem(1)
-    }
-
-    when (ivalid && !ovalid && empty ||
+    } .elsewhen (ivalid && !ovalid && empty ||
           ivalid && ovalid && !full) {
       mem(0) := io.in.bits
+    } .otherwise {
+      mem(0) := mem(0)
     }
 
     when (ivalid && !ovalid && !empty ||
@@ -93,6 +93,8 @@
 
     when (ivalid) {
       mem(0) := io.in.bits
+    } .otherwise {
+      mem(0) := mem(0)
     }
 
     io.value(0).valid := !empty