| commit | 5ff18fad5d576098a714e7f3dace82ceb7826449 | [log] [tgz] |
|---|---|---|
| author | Yenkai Wang <ykwang@google.com> | Wed Dec 04 17:47:31 2024 -0600 |
| committer | Yenkai Wang <ykwang@google.com> | Wed Dec 04 17:52:31 2024 -0600 |
| tree | 950df0c9ea6ac11b48d7363b66a2999466aa40a1 | |
| parent | ef7ec3f7a90866e1a0a656d464392207222f7378 [diff] |
Fix the latch issue in Slice Change-Id: Id66ab87a8894cd0833e5e60134af9cae386158cb
Kelvin is a RISC-V32IM core with a custom instruction set.
More information on the design can be found in the overview.
Kelvin uses bazel as it's build system. The Verilated simulator for Kelvin can be generated using:
bazel build //tests/verilator_sim:core_sim
The verilog source for the Kelvin core can be generated using:
bazel build //hdl/chisel/src/kelvin:core_cc_library_emit_verilog
Verilog source for the Matcha SoC can be generated using:
bazel clean --expunge # To generate the ToT sha bazel build //hdl/chisel:matcha_kelvin_verilog