| commit | 5f52f0edda7086e1cae5070855db66a4f0a6458d | [log] [tgz] |
|---|---|---|
| author | Zhidong Liang <Zhidong.Liang@verisilicon.com> | Thu Jan 09 17:53:18 2025 +0800 |
| committer | Derek Chow <derekjchow@google.com> | Thu Jan 16 13:11:05 2025 -0800 |
| tree | dcdae29ad7308cc3a5ad7d8a1c395b62b891593c | |
| parent | af610eb39b11c759011f381993ce72c007ed8b7c [diff] |
Fix vrf index decoder for VV && vd_valid conditon Change-Id: I0951784eac9d16f5ba8c403b6f54be836ad12010
Kelvin is a RISC-V32IM core with a custom instruction set.
More information on the design can be found in the overview.
Kelvin uses bazel as it's build system. The Verilated simulator for Kelvin can be generated using:
bazel build //tests/verilator_sim:core_sim
The verilog source for the Kelvin core can be generated using:
bazel build //hdl/chisel/src/kelvin:core_cc_library_emit_verilog
Verilog source for the Matcha SoC can be generated using:
bazel clean --expunge # To generate the ToT sha bazel build //hdl/chisel:matcha_kelvin_verilog