Fix for loads > 8 steps In the backend: - Allow up to 32 uops - Decode affected instructions - Set vd offset for them - Set vs2 offset for them - Set segment_index for them All existing load-store tests now pass Change-Id: I2c77efd78d71dc418032b3d16f8c9297505dce37
Kelvin is a RISC-V32IM core with a custom instruction set.
More information on the design can be found in the overview.
Kelvin uses bazel as it's build system. The Verilated simulator for Kelvin can be generated using:
bazel build //tests/verilator_sim:core_sim
The verilog source for the Kelvin core can be generated using:
bazel build //hdl/chisel/src/kelvin:core_cc_library_emit_verilog
Verilog source for the Matcha SoC can be generated using:
bazel clean --expunge # To generate the ToT sha bazel build //hdl/chisel:matcha_kelvin_verilog