| commit | 4570a533bccb08df32de295931f69be12dc68d7f | [log] [tgz] |
|---|---|---|
| author | Alex Van Damme <atv@google.com> | Thu Jul 17 12:27:56 2025 -0700 |
| committer | Alex Van Damme <atv@google.com> | Thu Jul 17 12:41:03 2025 -0700 |
| tree | 305fd9880e2cab2fe486b7ba4d6413d839eea005 | |
| parent | ea45a72d381123f9735730f24214b8078e9d065b [diff] |
Fix(dispatch): Prevent FPU/LSU hazard in DispatchV1 A structural hazard exists in the V1 dispatcher where a floating-point operation could be dispatched in the same cycle as a floating-point store. This caused a resource conflict over the floating-point register file, leading to incorrect data being written to memory. This is resolved by adding an interlock that prevents a floating-point operation from being dispatched if the LSU is already active in the current dispatch group. This ensures that LSU and FPU operations are mutually exclusive, matching the correct behavior of DispatchV2. Change-Id: I0d4c0fce95be532cc4381636d6114edb95f6e800
Kelvin is a RISC-V32IM core with a custom instruction set.
More information on the design can be found in the overview.
Kelvin uses bazel as it's build system. The Verilated simulator for Kelvin can be generated using:
bazel build //tests/verilator_sim:core_sim
The verilog source for the Kelvin core can be generated using:
bazel build //hdl/chisel/src/kelvin:core_cc_library_emit_verilog
Verilog source for the Matcha SoC can be generated using:
bazel clean --expunge # To generate the ToT sha bazel build //hdl/chisel:matcha_kelvin_verilog