| commit | 43d08d620d8234b3a99ae980a5b2980ef5ce117e | [log] [tgz] |
|---|---|---|
| author | Tianyu Li <Tianyu.Li@verisilicon.com> | Tue Jan 14 15:22:05 2025 +0800 |
| committer | Derek Chow <derekjchow@google.com> | Tue Jan 21 13:40:31 2025 -0800 |
| tree | f65d5d8e4fcbcdd77a03f5244a576891f416dc08 | |
| parent | e7ac0dda5d7e7a839cb38b3905c0e4f212d726df [diff] |
adjust assertion Change-Id: Ie28df0a8094cbdb767f51b124016160b77e224e9
Kelvin is a RISC-V32IM core with a custom instruction set.
More information on the design can be found in the overview.
Kelvin uses bazel as it's build system. The Verilated simulator for Kelvin can be generated using:
bazel build //tests/verilator_sim:core_sim
The verilog source for the Kelvin core can be generated using:
bazel build //hdl/chisel/src/kelvin:core_cc_library_emit_verilog
Verilog source for the Matcha SoC can be generated using:
bazel clean --expunge # To generate the ToT sha bazel build //hdl/chisel:matcha_kelvin_verilog