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opensecura / hw / kelvin / dfae871cf536ca69b522223194a3ed22e17a791a
commitdfae871cf536ca69b522223194a3ed22e17a791a[log] [tgz]
authorDerek Chow <derekjchow@google.com>Wed Sep 03 17:59:09 2025 -0700
committerDerek Chow <derekjchow@google.com>Wed Sep 03 19:04:14 2025 -0700
tree68e67b28417bc65ece551f652f41a47a58854dca
parent2affd50913a921de700444d52189c8a42fc4e460 [diff]
Apply masks to all write ports.

Change-Id: If9636c190777ed28bc52b9f881ffa4a56878f11e
2 files changed
tree: 68e67b28417bc65ece551f652f41a47a58854dca
  1. doc/
  2. examples/
  3. external/
  4. fpga/
  5. hdl/
  6. hw_sim/
  7. kelvin_test_utils/
  8. lib/
  9. platforms/
  10. rules/
  11. tests/
  12. third_party/
  13. toolchain/
  14. utils/
  15. .bazelrc
  16. .bazelversion
  17. .gitignore
  18. CONTRIBUTING.md
  19. LICENSE
  20. PREUPLOAD.cfg
  21. README.md
  22. WORKSPACE
README.md

Kelvin

Kelvin is a RISC-V32IM core with a custom instruction set.

Kelvin block diagram

More information on the design can be found in the overview.

Getting Started

  • If you are hardware engineer looking to integrate Kelvin into your design, check out our integration guide.
  • If you are a software engineer looking to write code for Kelvin, start with this tutorial.

Building

Kelvin uses bazel as it's build system. The Verilated simulator for Kelvin can be generated using:

bazel build //tests/verilator_sim:core_sim

The verilog source for the Kelvin core can be generated using:

bazel build //hdl/chisel/src/kelvin:core_cc_library_emit_verilog

Verilog source for the Matcha SoC can be generated using:

bazel clean --expunge  # To generate the ToT sha
bazel build //hdl/chisel:matcha_kelvin_verilog