[rvvi] Handle vd conflicts for vector tracing - Multiple vector instructions can be dispatched concurrently with the same destination register. Update our retirement logic to only consume one write to a given register, per cycle. Change-Id: I1acf2ac2db19d3d048f295ac754d9ffc23cbd075
Kelvin is a RISC-V32IM core with a custom instruction set.
More information on the design can be found in the overview.
Kelvin uses bazel as it's build system. The Verilated simulator for Kelvin can be generated using:
bazel build //tests/verilator_sim:core_sim
The verilog source for the Kelvin core can be generated using:
bazel build //hdl/chisel/src/kelvin:core_cc_library_emit_verilog
Verilog source for the Matcha SoC can be generated using:
bazel clean --expunge # To generate the ToT sha bazel build //hdl/chisel:matcha_kelvin_verilog