| commit | 38e3297f3f8b6037980a9e2a9962cfa846e9463a | [log] [tgz] |
|---|---|---|
| author | Alex Van Damme <atv@google.com> | Fri Sep 12 16:23:09 2025 -0700 |
| committer | Derek Chow <derekjchow@google.com> | Thu Sep 18 18:14:03 2025 -0700 |
| tree | 5151c14755fef516b5906670040d1c0f927d4387 | |
| parent | c2c02f7ed3decad9fbb33e24fb2c59cc926e4a8d [diff] |
[rvvi] Handle vd conflicts for vector tracing - Multiple vector instructions can be dispatched concurrently with the same destination register. Update our retirement logic to only consume one write to a given register, per cycle. Change-Id: I1acf2ac2db19d3d048f295ac754d9ffc23cbd075
Kelvin is a RISC-V32IM core with a custom instruction set.
More information on the design can be found in the overview.
Kelvin uses bazel as it's build system. The Verilated simulator for Kelvin can be generated using:
bazel build //tests/verilator_sim:core_sim
The verilog source for the Kelvin core can be generated using:
bazel build //hdl/chisel/src/kelvin:core_cc_library_emit_verilog
Verilog source for the Matcha SoC can be generated using:
bazel clean --expunge # To generate the ToT sha bazel build //hdl/chisel:matcha_kelvin_verilog