Upgrade to Chisel 5.1.0
- Additionally, update verilator in rules_hdl to v4.226, to sync w/ the
suggestion version from Chisel.
Change-Id: I077d75417c3230777c656ebff59f999f0effeb27
diff --git a/WORKSPACE b/WORKSPACE
index fa5bbf9..be6e23e 100644
--- a/WORKSPACE
+++ b/WORKSPACE
@@ -5,7 +5,7 @@
# Scala setup
load("@io_bazel_rules_scala//:scala_config.bzl", "scala_config")
-scala_config(scala_version = "2.13.6")
+scala_config(scala_version = "2.13.11")
load("@io_bazel_rules_scala//scala:scala.bzl", "rules_scala_setup", "rules_scala_toolchain_deps_repositories")
rules_scala_setup()
rules_scala_toolchain_deps_repositories(fetch_sources = True)
diff --git a/external/0004-Build-verilator-v4.210.patch b/external/0004-Build-verilator-v4.210.patch
deleted file mode 100644
index 98aa675..0000000
--- a/external/0004-Build-verilator-v4.210.patch
+++ /dev/null
@@ -1,94 +0,0 @@
-From b5db9a82ba3557a08c9d4ff27aaa068fc6acb5c4 Mon Sep 17 00:00:00 2001
-From: Cindy Liu <hcindyl@google.com>
-Date: Fri, 25 Aug 2023 23:41:55 -0700
-Subject: [PATCH] Build verilator v4.210
-
----
- dependency_support/verilator/verilator.BUILD | 9 ++-------
- dependency_support/verilator/verilator.bzl | 5 +++--
- 2 files changed, 5 insertions(+), 9 deletions(-)
-
-diff --git dependency_support/verilator/verilator.BUILD dependency_support/verilator/verilator.BUILD
-index 00fd758..596fd90 100644
---- dependency_support/verilator/verilator.BUILD
-+++ dependency_support/verilator/verilator.BUILD
-@@ -49,7 +49,6 @@ genrule(
- "V3Ast__gen_report.txt",
- "V3Ast__gen_types.h",
- "V3Ast__gen_visitor.h",
-- "V3Ast__gen_yystype.h",
- "V3AstNodes__gen_macros.h",
- ],
- cmd = """
-@@ -59,7 +58,6 @@ genrule(
- cp V3Ast__gen_report.txt $(@D)
- cp V3Ast__gen_types.h $(@D)
- cp V3Ast__gen_visitor.h $(@D)
-- cp V3Ast__gen_yystype.h $(@D)
- cp V3AstNodes__gen_macros.h $(@D)
- """,
- )
-@@ -150,12 +148,11 @@ cc_library(
- "src/V3Const.cpp",
- ],
- ) + [
-+ ":V3AstNodes__gen_macros.h",
- ":V3Ast__gen_classes.h",
- ":V3Ast__gen_impl.h",
- ":V3Ast__gen_types.h",
- ":V3Ast__gen_visitor.h",
-- ":V3AstNodes__gen_macros.h",
-- ":V3Ast__gen_yystype.h",
- ":V3Const__gen.cpp",
- ":V3ParseBison.h",
- ],
-@@ -214,12 +211,9 @@ cc_library(
- "include/verilated_trace.h",
- "include/verilated_trace_defs.h",
- # Needed for verilated_vcd_c.cpp and verilated_fst_c.cpp
-- "include/verilated_trace_imp.h",
- "include/verilated_vcd_c.h",
- "include/verilated_vcd_sc.h",
- "include/verilatedos.h",
-- "include/verilated_types.h",
-- "include/verilated_funcs.h",
- ],
- # TODO: Remove these once upstream fixes these warnings
- copts = ["-Wno-unused-const-variable"],
-@@ -233,6 +227,7 @@ cc_library(
- "include/gtkwave/fastlz.c",
- "include/gtkwave/fstapi.c",
- "include/gtkwave/lz4.c",
-+ "include/verilated_trace_imp.cpp",
- ],
- visibility = ["//visibility:public"],
- deps = [
-diff --git dependency_support/verilator/verilator.bzl dependency_support/verilator/verilator.bzl
-index 76893b7..8f98905 100644
---- dependency_support/verilator/verilator.bzl
-+++ dependency_support/verilator/verilator.bzl
-@@ -23,6 +23,7 @@ def _verilator_repository_impl(ctx):
- stripPrefix = "verilator-{}".format(ctx.attr.version),
- )
-
-+ ctx.patch(Label("@kelvin_hw//external:0005-Fix-verilator-v4.210-build-errors.patch"))
- ctx.file("WORKSPACE", "workspace(name = {name})\n".format(name = repr(ctx.name)))
- ctx.symlink(ctx.attr._buildfile, "BUILD")
-
-@@ -56,11 +57,11 @@ verilator_repository = repository_rule(
- ),
- "version": attr.string(
- doc = "The version of verilator to use.",
-- default = "4.224",
-+ default = "4.210",
- ),
- "sha256": attr.string(
- doc = "The sha256 hash for this version of verilator",
-- default = "010ff2b5c76d4dbc2ed4a3278a5599ba35c8ed4c05690e57296d6b281591367b",
-+ default = "3a2e6f27a5d80116a268ba054a3be61aca924bc54c5556ea25e75ee974201abb",
- ),
- },
- )
---
-2.42.0.rc2.253.gd59a3bf2b4-goog
-
diff --git a/external/0004-Build-verilator-v4.226.patch b/external/0004-Build-verilator-v4.226.patch
new file mode 100644
index 0000000..9154577
--- /dev/null
+++ b/external/0004-Build-verilator-v4.226.patch
@@ -0,0 +1,52 @@
+diff --git dependency_support/verilator/verilator.BUILD dependency_support/verilator/verilator.BUILD
+index 00fd758..5c93a65 100644
+--- dependency_support/verilator/verilator.BUILD
++++ dependency_support/verilator/verilator.BUILD
+@@ -48,7 +48,8 @@ genrule(
+ "V3Ast__gen_impl.h",
+ "V3Ast__gen_report.txt",
+ "V3Ast__gen_types.h",
+- "V3Ast__gen_visitor.h",
++ "V3Ast__gen_visitor_decls.h",
++ "V3Ast__gen_visitor_defns.h",
+ "V3Ast__gen_yystype.h",
+ "V3AstNodes__gen_macros.h",
+ ],
+@@ -58,7 +59,8 @@ genrule(
+ cp V3Ast__gen_impl.h $(@D)
+ cp V3Ast__gen_report.txt $(@D)
+ cp V3Ast__gen_types.h $(@D)
+- cp V3Ast__gen_visitor.h $(@D)
++ cp V3Ast__gen_visitor_decls.h $(@D)
++ cp V3Ast__gen_visitor_defns.h $(@D)
+ cp V3Ast__gen_yystype.h $(@D)
+ cp V3AstNodes__gen_macros.h $(@D)
+ """,
+@@ -153,7 +155,8 @@ cc_library(
+ ":V3Ast__gen_classes.h",
+ ":V3Ast__gen_impl.h",
+ ":V3Ast__gen_types.h",
+- ":V3Ast__gen_visitor.h",
++ ":V3Ast__gen_visitor_decls.h",
++ ":V3Ast__gen_visitor_defns.h",
+ ":V3AstNodes__gen_macros.h",
+ ":V3Ast__gen_yystype.h",
+ ":V3Const__gen.cpp",
+diff --git dependency_support/verilator/verilator.bzl dependency_support/verilator/verilator.bzl
+index 76893b7..1dd2d5e 100644
+--- dependency_support/verilator/verilator.bzl
++++ dependency_support/verilator/verilator.bzl
+@@ -56,11 +56,11 @@ verilator_repository = repository_rule(
+ ),
+ "version": attr.string(
+ doc = "The version of verilator to use.",
+- default = "4.224",
++ default = "4.226",
+ ),
+ "sha256": attr.string(
+ doc = "The sha256 hash for this version of verilator",
+- default = "010ff2b5c76d4dbc2ed4a3278a5599ba35c8ed4c05690e57296d6b281591367b",
++ default = "70bc941d86e4810253d51aa94898b0802d916ab76296a398f8ceb8798122c9be",
+ ),
+ },
+ )
diff --git a/hdl/chisel/BUILD b/hdl/chisel/BUILD
index cdae970..42deab7 100644
--- a/hdl/chisel/BUILD
+++ b/hdl/chisel/BUILD
@@ -179,13 +179,13 @@
genrule(
name = "matcha_kelvin_verilog",
srcs = [
- ":Kelvin.v",
+ ":Kelvin.sv",
"//hdl/verilog:ClockGate.v",
"//hdl/verilog:Sram_1rw_256x256.v",
"//hdl/verilog:Sram_1rwm_256x288.v",
],
outs = [
- "kelvin.v",
+ "kelvin.sv",
"ClockGate.v",
"Sram_1rw_256x256.v",
"Sram_1rwm_256x288.v",
@@ -195,8 +195,8 @@
cmd = """
echo "\\`define STOP_COND 0
\\`define PRINTF_COND 0
-" > $(location kelvin.v)
- cat $(location Kelvin.v) >> $(location kelvin.v)
+" > $(location kelvin.sv)
+ cat $(location Kelvin.sv) >> $(location kelvin.sv)
cp -f $(location //hdl/verilog:ClockGate.v) $(location ClockGate.v)
cp -f $(location //hdl/verilog:Sram_1rw_256x256.v) $(location Sram_1rw_256x256.v)
cp -f $(location //hdl/verilog:Sram_1rwm_256x288.v) $(location Sram_1rwm_256x288.v)
diff --git a/hdl/chisel/kelvin.core.in b/hdl/chisel/kelvin.core.in
index 5aa27ae..e8d61c6 100644
--- a/hdl/chisel/kelvin.core.in
+++ b/hdl/chisel/kelvin.core.in
@@ -7,7 +7,7 @@
filesets:
files_rtl:
files:
- - kelvin.v
+ - kelvin.sv
- ClockGate.v
- Sram_1rw_256x256.v
- Sram_1rwm_256x288.v
diff --git a/hdl/chisel/src/common/Fifo.scala b/hdl/chisel/src/common/Fifo.scala
index 155266f..8c653b2 100644
--- a/hdl/chisel/src/common/Fifo.scala
+++ b/hdl/chisel/src/common/Fifo.scala
@@ -16,6 +16,7 @@
import chisel3._
import chisel3.util._
+import _root_.circt.stage.ChiselStage
object Fifo {
def apply[T <: Data](t: T, n: Int, passReady: Boolean = false) = {
@@ -108,9 +109,9 @@
}
object EmitFifo extends App {
- (new chisel3.stage.ChiselStage).emitVerilog(new Fifo(UInt(8.W), 11, false), args)
+ ChiselStage.emitSystemVerilogFile(new Fifo(UInt(8.W), 11, false), args)
}
object EmitFifo_1 extends App {
- (new chisel3.stage.ChiselStage).emitVerilog(new Fifo(UInt(8.W), 11, true), args)
+ ChiselStage.emitSystemVerilogFile(new Fifo(UInt(8.W), 11, true), args)
}
diff --git a/hdl/chisel/src/common/Fifo4.scala b/hdl/chisel/src/common/Fifo4.scala
index 952ff33..a89ab0f 100644
--- a/hdl/chisel/src/common/Fifo4.scala
+++ b/hdl/chisel/src/common/Fifo4.scala
@@ -16,6 +16,7 @@
import chisel3._
import chisel3.util._
+import _root_.circt.stage.ChiselStage
object Fifo4 {
def apply[T <: Data](t: T, n: Int) = {
@@ -188,5 +189,5 @@
}
object EmitFifo4 extends App {
- (new chisel3.stage.ChiselStage).emitVerilog(new Fifo4(UInt(8.W), 11), args)
+ ChiselStage.emitSystemVerilogFile(new Fifo4(UInt(8.W), 11), args)
}
diff --git a/hdl/chisel/src/common/Fifo4e.scala b/hdl/chisel/src/common/Fifo4e.scala
index a298552..0d8a1cd 100644
--- a/hdl/chisel/src/common/Fifo4e.scala
+++ b/hdl/chisel/src/common/Fifo4e.scala
@@ -16,6 +16,7 @@
import chisel3._
import chisel3.util._
+import _root_.circt.stage.ChiselStage
// Fifo4 with entry output and no output registration stage.
@@ -143,5 +144,5 @@
}
object EmitFifo4e extends App {
- (new chisel3.stage.ChiselStage).emitVerilog(new Fifo4e(UInt(8.W), 10), args)
+ ChiselStage.emitSystemVerilogFile(new Fifo4e(UInt(8.W), 10), args)
}
diff --git a/hdl/chisel/src/common/Fifo4x4.scala b/hdl/chisel/src/common/Fifo4x4.scala
index 656d2c6..064af4b 100644
--- a/hdl/chisel/src/common/Fifo4x4.scala
+++ b/hdl/chisel/src/common/Fifo4x4.scala
@@ -16,6 +16,7 @@
import chisel3._
import chisel3.util._
+import _root_.circt.stage.ChiselStage
object Fifo4x4 {
def apply[T <: Data](t: T, n: Int) = {
@@ -193,5 +194,5 @@
}
object EmitFifo4x4 extends App {
- (new chisel3.stage.ChiselStage).emitVerilog(new Fifo4x4(UInt(32.W), 24), args)
+ ChiselStage.emitSystemVerilogFile(new Fifo4x4(UInt(32.W), 24), args)
}
diff --git a/hdl/chisel/src/common/IDiv.scala b/hdl/chisel/src/common/IDiv.scala
index aa2e660..4532b7b 100644
--- a/hdl/chisel/src/common/IDiv.scala
+++ b/hdl/chisel/src/common/IDiv.scala
@@ -17,6 +17,7 @@
import chisel3._
import chisel3.util._
import common._
+import _root_.circt.stage.ChiselStage
// An integer divide unit, to be fused with fdiv.
@@ -185,5 +186,5 @@
}
object EmitIDiv extends App {
- (new chisel3.stage.ChiselStage).emitVerilog(new IDiv(1), args)
+ ChiselStage.emitSystemVerilogFile(new IDiv(1), args)
}
diff --git a/hdl/chisel/src/common/Library.scala b/hdl/chisel/src/common/Library.scala
index f3ab5aa..3c69d1d 100644
--- a/hdl/chisel/src/common/Library.scala
+++ b/hdl/chisel/src/common/Library.scala
@@ -19,7 +19,7 @@
object MuxOR {
def apply(valid: Bool, data: UInt): UInt = {
- Mux(valid, data, 0.U(data.getWidth))
+ Mux(valid, data, 0.U(data.getWidth.W))
}
def apply(valid: Bool, data: Bool): Bool = {
diff --git a/hdl/chisel/src/common/Slice.scala b/hdl/chisel/src/common/Slice.scala
index 5895e52..549ba17 100644
--- a/hdl/chisel/src/common/Slice.scala
+++ b/hdl/chisel/src/common/Slice.scala
@@ -16,6 +16,7 @@
import chisel3._
import chisel3.util._
+import _root_.circt.stage.ChiselStage
object Slice {
def apply[T <: Data](t: T, doubleBuffered: Boolean = true,
@@ -110,33 +111,33 @@
}
object EmitSlice extends App {
- (new chisel3.stage.ChiselStage).emitVerilog(new Slice(UInt(32.W), false, false, false), args)
+ ChiselStage.emitSystemVerilogFile(new Slice(UInt(32.W), false, false, false), args)
}
object EmitSlice_1 extends App {
- (new chisel3.stage.ChiselStage).emitVerilog(new Slice(UInt(32.W), false, false, true), args)
+ ChiselStage.emitSystemVerilogFile(new Slice(UInt(32.W), false, false, true), args)
}
object EmitSlice_2 extends App {
- (new chisel3.stage.ChiselStage).emitVerilog(new Slice(UInt(32.W), false, true, false), args)
+ ChiselStage.emitSystemVerilogFile(new Slice(UInt(32.W), false, true, false), args)
}
object EmitSlice_3 extends App {
- (new chisel3.stage.ChiselStage).emitVerilog(new Slice(UInt(32.W), false, true, true), args)
+ ChiselStage.emitSystemVerilogFile(new Slice(UInt(32.W), false, true, true), args)
}
object EmitSlice_4 extends App {
- (new chisel3.stage.ChiselStage).emitVerilog(new Slice(UInt(32.W), true, false, false), args)
+ ChiselStage.emitSystemVerilogFile(new Slice(UInt(32.W), true, false, false), args)
}
object EmitSlice_5 extends App {
- (new chisel3.stage.ChiselStage).emitVerilog(new Slice(UInt(32.W), true, false, true), args)
+ ChiselStage.emitSystemVerilogFile(new Slice(UInt(32.W), true, false, true), args)
}
object EmitSlice_6 extends App {
- (new chisel3.stage.ChiselStage).emitVerilog(new Slice(UInt(32.W), true, true, false), args)
+ ChiselStage.emitSystemVerilogFile(new Slice(UInt(32.W), true, true, false), args)
}
object EmitSlice_7 extends App {
- (new chisel3.stage.ChiselStage).emitVerilog(new Slice(UInt(32.W), true, true, true), args)
+ ChiselStage.emitSystemVerilogFile(new Slice(UInt(32.W), true, true, true), args)
}
diff --git a/hdl/chisel/src/kelvin/Core.scala b/hdl/chisel/src/kelvin/Core.scala
index 2c72f9c..ee59964 100644
--- a/hdl/chisel/src/kelvin/Core.scala
+++ b/hdl/chisel/src/kelvin/Core.scala
@@ -17,6 +17,7 @@
import chisel3._
import chisel3.util._
import common._
+import _root_.circt.stage.ChiselStage
object Core {
def apply(p: Parameters): Core = {
@@ -86,5 +87,5 @@
object EmitCore extends App {
val p = new Parameters
- (new chisel3.stage.ChiselStage).emitVerilog(new Core(p), args)
+ ChiselStage.emitSystemVerilogFile(new Core(p), args)
}
diff --git a/hdl/chisel/src/kelvin/DBus2Axi.scala b/hdl/chisel/src/kelvin/DBus2Axi.scala
index 68aba80..55ae7db 100644
--- a/hdl/chisel/src/kelvin/DBus2Axi.scala
+++ b/hdl/chisel/src/kelvin/DBus2Axi.scala
@@ -17,6 +17,7 @@
import chisel3._
import chisel3.util._
import common._
+import _root_.circt.stage.ChiselStage
object DBus2Axi {
def apply(p: Parameters): DBus2Axi = {
@@ -75,5 +76,5 @@
object EmitDBus2Axi extends App {
val p = new Parameters
- (new chisel3.stage.ChiselStage).emitVerilog(new DBus2Axi(p), args)
+ ChiselStage.emitSystemVerilogFile(new DBus2Axi(p), args)
}
diff --git a/hdl/chisel/src/kelvin/DBusMux.scala b/hdl/chisel/src/kelvin/DBusMux.scala
index 8c9c566..7b89e3e 100644
--- a/hdl/chisel/src/kelvin/DBusMux.scala
+++ b/hdl/chisel/src/kelvin/DBusMux.scala
@@ -17,6 +17,7 @@
import chisel3._
import chisel3.util._
import common._
+import _root_.circt.stage.ChiselStage
object DBusMux {
def apply(p: Parameters): DBusMux = {
@@ -51,5 +52,5 @@
object EmitDBusMux extends App {
val p = new Parameters
- (new chisel3.stage.ChiselStage).emitVerilog(new DBusMux(p), args)
+ ChiselStage.emitSystemVerilogFile(new DBusMux(p), args)
}
diff --git a/hdl/chisel/src/kelvin/L1DCache.scala b/hdl/chisel/src/kelvin/L1DCache.scala
index 4c0d8d0..94d88ae 100644
--- a/hdl/chisel/src/kelvin/L1DCache.scala
+++ b/hdl/chisel/src/kelvin/L1DCache.scala
@@ -18,6 +18,7 @@
import chisel3.util._
import chisel3.experimental.ChiselEnum
import common._
+import _root_.circt.stage.ChiselStage
object L1DCache {
def apply(p: Parameters): L1DCache = {
@@ -690,10 +691,10 @@
object EmitL1DCache extends App {
val p = new Parameters
- (new chisel3.stage.ChiselStage).emitVerilog(new L1DCache(p), args)
+ ChiselStage.emitSystemVerilogFile(new L1DCache(p), args)
}
object EmitL1DCacheBank extends App {
val p = new Parameters
- (new chisel3.stage.ChiselStage).emitVerilog(new L1DCacheBank(p), args)
+ ChiselStage.emitSystemVerilogFile(new L1DCacheBank(p), args)
}
diff --git a/hdl/chisel/src/kelvin/L1ICache.scala b/hdl/chisel/src/kelvin/L1ICache.scala
index 135bb6c..90cb912 100644
--- a/hdl/chisel/src/kelvin/L1ICache.scala
+++ b/hdl/chisel/src/kelvin/L1ICache.scala
@@ -17,6 +17,7 @@
import chisel3._
import chisel3.util._
import common._
+import _root_.circt.stage.ChiselStage
object L1ICache {
def apply(p: Parameters): L1ICache = {
@@ -268,5 +269,5 @@
object EmitL1ICache extends App {
val p = new Parameters
- (new chisel3.stage.ChiselStage).emitVerilog(new L1ICache(p), args)
+ ChiselStage.emitSystemVerilogFile(new L1ICache(p), args)
}
diff --git a/hdl/chisel/src/kelvin/Library.scala b/hdl/chisel/src/kelvin/Library.scala
index cb887c2..26b92a3 100644
--- a/hdl/chisel/src/kelvin/Library.scala
+++ b/hdl/chisel/src/kelvin/Library.scala
@@ -19,7 +19,7 @@
object Mux0 {
def apply(valid: Bool, data: UInt): UInt = {
- Mux(valid, data, 0.U(data.getWidth))
+ Mux(valid, data, 0.U(data.getWidth.W))
}
def apply(valid: Bool, data: Bool): Bool = {
@@ -29,7 +29,7 @@
object MuxOR {
def apply(valid: Bool, data: UInt): UInt = {
- Mux(valid, data, 0.U(data.getWidth))
+ Mux(valid, data, 0.U(data.getWidth.W))
}
def apply(valid: Bool, data: Bool): Bool = {
diff --git a/hdl/chisel/src/kelvin/scalar/Dvu.scala b/hdl/chisel/src/kelvin/scalar/Dvu.scala
index caddba7..479b489 100644
--- a/hdl/chisel/src/kelvin/scalar/Dvu.scala
+++ b/hdl/chisel/src/kelvin/scalar/Dvu.scala
@@ -17,6 +17,7 @@
import chisel3._
import chisel3.util._
import common._
+import _root_.circt.stage.ChiselStage
object Dvu {
def apply(p: Parameters): Dvu = {
@@ -155,5 +156,5 @@
object EmitDvu extends App {
val p = new Parameters
- (new chisel3.stage.ChiselStage).emitVerilog(new Dvu(p), args)
+ ChiselStage.emitSystemVerilogFile(new Dvu(p), args)
}
diff --git a/hdl/chisel/src/kelvin/scalar/Fetch.scala b/hdl/chisel/src/kelvin/scalar/Fetch.scala
index fb951e1..e265dab 100644
--- a/hdl/chisel/src/kelvin/scalar/Fetch.scala
+++ b/hdl/chisel/src/kelvin/scalar/Fetch.scala
@@ -22,6 +22,7 @@
import chisel3._
import chisel3.util._
import common._
+import _root_.circt.stage.ChiselStage
object Fetch {
def apply(p: Parameters): Fetch = {
@@ -522,5 +523,5 @@
object EmitFetch extends App {
val p = new Parameters
- (new chisel3.stage.ChiselStage).emitVerilog(new Fetch(p), args)
+ ChiselStage.emitSystemVerilogFile(new Fetch(p), args)
}
diff --git a/hdl/chisel/src/kelvin/scalar/Mlu.scala b/hdl/chisel/src/kelvin/scalar/Mlu.scala
index 6826bc6..94293d7 100644
--- a/hdl/chisel/src/kelvin/scalar/Mlu.scala
+++ b/hdl/chisel/src/kelvin/scalar/Mlu.scala
@@ -17,6 +17,7 @@
import chisel3._
import chisel3.util._
import common._
+import _root_.circt.stage.ChiselStage
object Mlu {
def apply(p: Parameters): Mlu = {
@@ -150,5 +151,5 @@
object EmitMlu extends App {
val p = new Parameters
- (new chisel3.stage.ChiselStage).emitVerilog(new Mlu(p), args)
+ ChiselStage.emitSystemVerilogFile(new Mlu(p), args)
}
diff --git a/hdl/chisel/src/kelvin/scalar/Regfile.scala b/hdl/chisel/src/kelvin/scalar/Regfile.scala
index a3e9d84..5dd884a 100644
--- a/hdl/chisel/src/kelvin/scalar/Regfile.scala
+++ b/hdl/chisel/src/kelvin/scalar/Regfile.scala
@@ -21,6 +21,7 @@
import chisel3._
import chisel3.util._
import common._
+import _root_.circt.stage.ChiselStage
object Regfile {
def apply(p: Parameters): Regfile = {
@@ -265,5 +266,5 @@
object EmitRegfile extends App {
val p = new Parameters
- (new chisel3.stage.ChiselStage).emitVerilog(new Regfile(p), args)
+ ChiselStage.emitSystemVerilogFile(new Regfile(p), args)
}
diff --git a/hdl/chisel/src/kelvin/scalar/SCore.scala b/hdl/chisel/src/kelvin/scalar/SCore.scala
index b380584..0926de8 100644
--- a/hdl/chisel/src/kelvin/scalar/SCore.scala
+++ b/hdl/chisel/src/kelvin/scalar/SCore.scala
@@ -19,6 +19,7 @@
import chisel3._
import chisel3.util._
import common._
+import _root_.circt.stage.ChiselStage
object SCore {
def apply(p: Parameters): SCore = {
@@ -357,5 +358,5 @@
object EmitSCore extends App {
val p = new Parameters
- (new chisel3.stage.ChiselStage).emitVerilog(new SCore(p), args)
+ ChiselStage.emitSystemVerilogFile(new SCore(p), args)
}
diff --git a/hdl/chisel/src/kelvin/vector/VAlu.scala b/hdl/chisel/src/kelvin/vector/VAlu.scala
index 2264823..03eae95 100644
--- a/hdl/chisel/src/kelvin/vector/VAlu.scala
+++ b/hdl/chisel/src/kelvin/vector/VAlu.scala
@@ -19,6 +19,7 @@
import chisel3._
import chisel3.util._
import common._
+import _root_.circt.stage.ChiselStage
object VAlu {
def apply(p: Parameters): VAlu = {
@@ -407,5 +408,5 @@
object EmitVAlu extends App {
val p = new Parameters
- (new chisel3.stage.ChiselStage).emitVerilog(new VAlu(p), args)
+ ChiselStage.emitSystemVerilogFile(new VAlu(p), args)
}
diff --git a/hdl/chisel/src/kelvin/vector/VAluInt.scala b/hdl/chisel/src/kelvin/vector/VAluInt.scala
index 1d767f9..b919d5d 100644
--- a/hdl/chisel/src/kelvin/vector/VAluInt.scala
+++ b/hdl/chisel/src/kelvin/vector/VAluInt.scala
@@ -18,6 +18,7 @@
import chisel3._
import chisel3.util._
+import _root_.circt.stage.ChiselStage
// VAluInt is foremost an ML depthwise and activiation unit with pipelining
// behaviors optimized to this functionality. All operations are pipelined with
@@ -994,7 +995,7 @@
val xeq = cmp_a(m,l) === cmp_b(m,l)
val xne = cmp_a(m,l) =/= cmp_b(m,l)
- val slt = cmp_a(m,l).asSInt() < cmp_b(m,l).asSInt()
+ val slt = cmp_a(m,l).asSInt < cmp_b(m,l).asSInt
val ult = cmp_a(m,l) < cmp_b(m,l)
val sle = slt || xeq
val ule = ult || xeq
@@ -1542,5 +1543,5 @@
object EmitVAluInt extends App {
val p = new Parameters
- (new chisel3.stage.ChiselStage).emitVerilog(new VAluInt(p, 0), args)
+ ChiselStage.emitSystemVerilogFile(new VAluInt(p, 0), args)
}
diff --git a/hdl/chisel/src/kelvin/vector/VCmdq.scala b/hdl/chisel/src/kelvin/vector/VCmdq.scala
index 5ed357f..20e29b3 100644
--- a/hdl/chisel/src/kelvin/vector/VCmdq.scala
+++ b/hdl/chisel/src/kelvin/vector/VCmdq.scala
@@ -19,6 +19,7 @@
import chisel3._
import chisel3.util._
import common._
+import _root_.circt.stage.ChiselStage
// A queue of commands, reducing VDecodeBits to just the necessary fields.
// <fin> retains just the needed fields or modifications.
@@ -179,5 +180,5 @@
active
}
- (new chisel3.stage.ChiselStage).emitVerilog(new VCmdq(8, new VCmdqTestBundle, VCmdqTestFin, VCmdqTestFout, VCmdqTestFactive), args)
+ ChiselStage.emitSystemVerilogFile(new VCmdq(8, new VCmdqTestBundle, VCmdqTestFin, VCmdqTestFout, VCmdqTestFactive), args)
}
diff --git a/hdl/chisel/src/kelvin/vector/VConvAlu.scala b/hdl/chisel/src/kelvin/vector/VConvAlu.scala
index c0829fb..e3313d8 100644
--- a/hdl/chisel/src/kelvin/vector/VConvAlu.scala
+++ b/hdl/chisel/src/kelvin/vector/VConvAlu.scala
@@ -18,6 +18,7 @@
import chisel3._
import chisel3.util._
+import _root_.circt.stage.ChiselStage
object VConvAlu {
def apply(p: Parameters): VConvAlu = {
@@ -121,5 +122,5 @@
object EmitVConvAlu extends App {
val p = new Parameters
- (new chisel3.stage.ChiselStage).emitVerilog(new VConvAlu(p), args)
+ ChiselStage.emitSystemVerilogFile(new VConvAlu(p), args)
}
diff --git a/hdl/chisel/src/kelvin/vector/VConvCtrl.scala b/hdl/chisel/src/kelvin/vector/VConvCtrl.scala
index 2cfc273..1e017a4 100644
--- a/hdl/chisel/src/kelvin/vector/VConvCtrl.scala
+++ b/hdl/chisel/src/kelvin/vector/VConvCtrl.scala
@@ -19,6 +19,7 @@
import chisel3._
import chisel3.util._
import common._
+import _root_.circt.stage.ChiselStage
object VConvCtrl {
def apply(p: Parameters): VConvCtrl = {
@@ -209,5 +210,5 @@
object EmitVConvCtrl extends App {
val p = new Parameters
- (new chisel3.stage.ChiselStage).emitVerilog(new VConvCtrl(p), args)
+ ChiselStage.emitSystemVerilogFile(new VConvCtrl(p), args)
}
diff --git a/hdl/chisel/src/kelvin/vector/VDecode.scala b/hdl/chisel/src/kelvin/vector/VDecode.scala
index cb9f419..fa48723 100644
--- a/hdl/chisel/src/kelvin/vector/VDecode.scala
+++ b/hdl/chisel/src/kelvin/vector/VDecode.scala
@@ -19,6 +19,7 @@
import chisel3._
import chisel3.util._
import common.Fifo4x4
+import _root_.circt.stage.ChiselStage
object VDecode {
def apply(p: Parameters): VDecode = {
@@ -452,5 +453,5 @@
object EmitVDecode extends App {
val p = new Parameters
- (new chisel3.stage.ChiselStage).emitVerilog(new VDecode(p), args)
+ ChiselStage.emitSystemVerilogFile(new VDecode(p), args)
}
diff --git a/hdl/chisel/src/kelvin/vector/VDecodeInstruction.scala b/hdl/chisel/src/kelvin/vector/VDecodeInstruction.scala
index ad72b54..ebe85f9 100644
--- a/hdl/chisel/src/kelvin/vector/VDecodeInstruction.scala
+++ b/hdl/chisel/src/kelvin/vector/VDecodeInstruction.scala
@@ -18,6 +18,7 @@
import chisel3._
import chisel3.util._
+import _root_.circt.stage.ChiselStage
class VDecodeInstruction(p: Parameters) extends Module {
val dec = new VDecodeOp()
@@ -635,5 +636,5 @@
object EmitVDecodeInstruction extends App {
val p = new Parameters
- (new chisel3.stage.ChiselStage).emitVerilog(new VDecodeInstruction(p), args)
+ ChiselStage.emitSystemVerilogFile(new VDecodeInstruction(p), args)
}
diff --git a/hdl/chisel/src/kelvin/vector/VLd.scala b/hdl/chisel/src/kelvin/vector/VLd.scala
index fda657f..88b4d8d 100644
--- a/hdl/chisel/src/kelvin/vector/VLd.scala
+++ b/hdl/chisel/src/kelvin/vector/VLd.scala
@@ -19,6 +19,7 @@
import chisel3._
import chisel3.util._
import common._
+import _root_.circt.stage.ChiselStage
object VLd {
def apply(p: Parameters): VLd = {
@@ -171,5 +172,5 @@
object EmitVLd extends App {
val p = new Parameters
- (new chisel3.stage.ChiselStage).emitVerilog(new VLd(p), args)
+ ChiselStage.emitSystemVerilogFile(new VLd(p), args)
}
diff --git a/hdl/chisel/src/kelvin/vector/VLdSt.scala b/hdl/chisel/src/kelvin/vector/VLdSt.scala
index 0f32148..df6fadc 100644
--- a/hdl/chisel/src/kelvin/vector/VLdSt.scala
+++ b/hdl/chisel/src/kelvin/vector/VLdSt.scala
@@ -19,6 +19,7 @@
import chisel3._
import chisel3.util._
import common._
+import _root_.circt.stage.ChiselStage
object VLdSt {
def apply(p: Parameters): VLdSt = {
@@ -314,5 +315,5 @@
object EmitVLdSt extends App {
val p = new Parameters
- (new chisel3.stage.ChiselStage).emitVerilog(new VLdSt(p), args)
+ ChiselStage.emitSystemVerilogFile(new VLdSt(p), args)
}
diff --git a/hdl/chisel/src/kelvin/vector/VRegfile.scala b/hdl/chisel/src/kelvin/vector/VRegfile.scala
index db7396d..523c7a0 100644
--- a/hdl/chisel/src/kelvin/vector/VRegfile.scala
+++ b/hdl/chisel/src/kelvin/vector/VRegfile.scala
@@ -19,6 +19,7 @@
import chisel3._
import chisel3.util._
import common._
+import _root_.circt.stage.ChiselStage
object VRegfile {
def apply(p: Parameters): VRegfile = {
@@ -442,5 +443,5 @@
object EmitVRegfile extends App {
val p = new Parameters
- (new chisel3.stage.ChiselStage).emitVerilog(new VRegfile(p), args)
+ ChiselStage.emitSystemVerilogFile(new VRegfile(p), args)
}
diff --git a/hdl/chisel/src/kelvin/vector/VRegfileSegment.scala b/hdl/chisel/src/kelvin/vector/VRegfileSegment.scala
index e4e17b2..90a4935 100644
--- a/hdl/chisel/src/kelvin/vector/VRegfileSegment.scala
+++ b/hdl/chisel/src/kelvin/vector/VRegfileSegment.scala
@@ -18,6 +18,7 @@
import chisel3._
import chisel3.util._
+import _root_.circt.stage.ChiselStage
class VRegfileSegment(p: Parameters) extends Module {
val readPorts = 7
@@ -115,5 +116,5 @@
object EmitVRegfileSegment extends App {
val p = new Parameters
- (new chisel3.stage.ChiselStage).emitVerilog(new VRegfileSegment(p), args)
+ ChiselStage.emitSystemVerilogFile(new VRegfileSegment(p), args)
}
diff --git a/hdl/chisel/src/kelvin/vector/VSt.scala b/hdl/chisel/src/kelvin/vector/VSt.scala
index 91b5565..9dcd9de 100644
--- a/hdl/chisel/src/kelvin/vector/VSt.scala
+++ b/hdl/chisel/src/kelvin/vector/VSt.scala
@@ -19,6 +19,7 @@
import chisel3._
import chisel3.util._
import common._
+import _root_.circt.stage.ChiselStage
object VSt {
def apply(p: Parameters): VSt = {
@@ -321,5 +322,5 @@
object EmitVSt extends App {
val p = new Parameters
- (new chisel3.stage.ChiselStage).emitVerilog(new VSt(p), args)
+ ChiselStage.emitSystemVerilogFile(new VSt(p), args)
}
diff --git a/hdl/chisel/src/matcha/Axi2Sram.scala b/hdl/chisel/src/matcha/Axi2Sram.scala
index 9926b7b..38914d5 100644
--- a/hdl/chisel/src/matcha/Axi2Sram.scala
+++ b/hdl/chisel/src/matcha/Axi2Sram.scala
@@ -17,6 +17,7 @@
import chisel3._
import chisel3.util._
import common._
+import _root_.circt.stage.ChiselStage
object Axi2Sram {
def apply(p: kelvin.Parameters): Axi2Sram = {
@@ -267,5 +268,5 @@
object EmitAxi2Sram extends App {
val p = new kelvin.Parameters
- (new chisel3.stage.ChiselStage).emitVerilog(new Axi2Sram(p), args)
+ ChiselStage.emitSystemVerilogFile(new Axi2Sram(p), args)
}
diff --git a/hdl/chisel/src/matcha/Crossbar.scala b/hdl/chisel/src/matcha/Crossbar.scala
index 93a213b..b9b24b9 100644
--- a/hdl/chisel/src/matcha/Crossbar.scala
+++ b/hdl/chisel/src/matcha/Crossbar.scala
@@ -16,6 +16,7 @@
import chisel3._
import chisel3.util._
+import _root_.circt.stage.ChiselStage
object Crossbar {
def apply(ports: Int, addrbits: Int, databits: Int, idbits: Int) = {
@@ -69,7 +70,7 @@
val amsb = addrbits - 1
val indexbits = addrbits - alsb
- withReset(reset.asAsyncReset()) {
+ withReset(reset.asAsyncReset) {
// ---------------------------------------------------------------------------
// Arbitrate.
val csel0 = RegInit(1.U(ports.W))
@@ -207,5 +208,5 @@
object EmitCrossbar extends App {
// 4MB = 2^22 = 2^17 * 256/8
- (new chisel3.stage.ChiselStage).emitVerilog(new Crossbar(4, 22, 256, 8), args)
+ ChiselStage.emitSystemVerilogFile(new Crossbar(4, 22, 256, 8), args)
}
diff --git a/hdl/chisel/src/matcha/Kelvin.scala b/hdl/chisel/src/matcha/Kelvin.scala
index 091aadb..65c8da0 100644
--- a/hdl/chisel/src/matcha/Kelvin.scala
+++ b/hdl/chisel/src/matcha/Kelvin.scala
@@ -17,6 +17,7 @@
import chisel3._
import chisel3.util._
import common._
+import _root_.circt.stage.ChiselStage
object Kelvin {
def apply(p: kelvin.Parameters): Kelvin = {
@@ -67,7 +68,7 @@
// This hybrid design allows for interfaces to reset immediately on reset
// assertion while ensuring all internal state will eventually be reset
// correctly before usage.
- val rst_i = (!rst_ni.asBool() || ml_reset).asAsyncReset()
+ val rst_i = (!rst_ni.asBool || ml_reset).asAsyncReset
val rst_core = Wire(Bool())
withClockAndReset(clk_i, rst_i) {
@@ -80,7 +81,7 @@
// ---------------------------------------------------------------------------
// Connect clock and reset.
- withClockAndReset(clk_g, rst_core.asAsyncReset()) {
+ withClockAndReset(clk_g, rst_core.asAsyncReset) {
assert(p.vectorBits == 256)
val core = kelvin.Core(p)
@@ -140,5 +141,5 @@
object EmitKelvin extends App {
val p = new kelvin.Parameters()
- (new chisel3.stage.ChiselStage).emitVerilog(new Kelvin(p), args)
+ ChiselStage.emitSystemVerilogFile(new Kelvin(p), args)
}
diff --git a/lib/BUILD b/lib/BUILD
index 90059a6..697589c 100644
--- a/lib/BUILD
+++ b/lib/BUILD
@@ -17,40 +17,43 @@
scala_library(
name = "chisel_lib",
scalacopts = [
- "-Xplugin:$(execpath @edu_berkeley_cs_chisel3_plugin//jar)",
- "-P:chiselplugin:genBundleElements",
+ "-Xplugin:$(execpath @org_chipsalliance_chisel_plugin//jar)",
],
visibility = ["//visibility:public"],
exports = [
"@com_github_scopt//jar",
+ "@com_lihaoyi_geny//jar",
+ "@com_lihaoyi_os_lib//jar",
+ "@com_lihaoyi_upickle//jar",
"@com_thoughtworks_paranamer//jar",
- "@edu_berkeley_cs_chisel3//jar",
- "@edu_berkeley_cs_chisel3_core//jar",
- "@edu_berkeley_cs_chisel3_macros//jar",
- "@edu_berkeley_cs_chisel3_plugin//jar",
- "@edu_berkeley_cs_firrtl//jar",
+ "@io_github_alexarchambault_data_class//jar",
"@net_jcazevedo_moultingyaml//jar",
"@org_apache_commons_commons_lang3//jar",
"@org_apache_commons_commons_text//jar",
+ "@org_chipsalliance_chisel//jar",
+ "@org_chipsalliance_chisel_plugin//jar",
"@org_json4s_json4s_ast//jar",
"@org_json4s_json4s_core//jar",
"@org_json4s_json4s_native//jar",
"@org_json4s_json4s_scalap//jar",
+ "@org_scala_lang_scala_reflect//jar",
],
deps = [
"@com_github_scopt//jar",
+ "@com_lihaoyi_geny//jar",
+ "@com_lihaoyi_os_lib//jar",
+ "@com_lihaoyi_upickle//jar",
"@com_thoughtworks_paranamer//jar",
- "@edu_berkeley_cs_chisel3//jar",
- "@edu_berkeley_cs_chisel3_core//jar",
- "@edu_berkeley_cs_chisel3_macros//jar",
- "@edu_berkeley_cs_chisel3_plugin//jar",
- "@edu_berkeley_cs_firrtl//jar",
+ "@io_github_alexarchambault_data_class//jar",
"@net_jcazevedo_moultingyaml//jar",
"@org_apache_commons_commons_lang3//jar",
"@org_apache_commons_commons_text//jar",
+ "@org_chipsalliance_chisel//jar",
+ "@org_chipsalliance_chisel_plugin//jar",
"@org_json4s_json4s_ast//jar",
"@org_json4s_json4s_core//jar",
"@org_json4s_json4s_native//jar",
"@org_json4s_json4s_scalap//jar",
+ "@org_scala_lang_scala_reflect//jar",
],
)
diff --git a/rules/chisel.bzl b/rules/chisel.bzl
index b101108..53967ab 100644
--- a/rules/chisel.bzl
+++ b/rules/chisel.bzl
@@ -18,6 +18,17 @@
load("@kelvin_hw//rules:verilator.bzl", "verilator_cc_library")
load("@rules_hdl//verilog:providers.bzl", "verilog_library")
+SCALA_COPTS = [
+ "-Ymacro-annotations",
+ "-Xplugin:$(execpath @org_chipsalliance_chisel_plugin//jar)",
+ "-explaintypes",
+ "-feature",
+ "-language:reflectiveCalls",
+ "-unchecked",
+ "-Xcheckinit",
+ "-Xlint:infer-any",
+]
+
def chisel_library(
name,
srcs = [],
@@ -28,12 +39,9 @@
srcs = srcs,
deps = [
"@kelvin_hw//lib:chisel_lib",
- "@edu_berkeley_cs_chisel3_plugin//jar",
+ "@org_chipsalliance_chisel_plugin//jar",
] + deps,
- scalacopts = [
- "-Xplugin:$(execpath @edu_berkeley_cs_chisel3_plugin//jar)",
- "-P:chiselplugin:genBundleElements",
- ],
+ scalacopts = SCALA_COPTS,
visibility = visibility,
)
@@ -49,12 +57,9 @@
main_class = main_class,
deps = [
"@kelvin_hw//lib:chisel_lib",
- "@edu_berkeley_cs_chisel3_plugin//jar",
+ "@org_chipsalliance_chisel_plugin//jar",
] + deps,
- scalacopts = [
- "-Xplugin:$(execpath @edu_berkeley_cs_chisel3_plugin//jar)",
- "-P:chiselplugin:genBundleElements",
- ],
+ scalacopts = SCALA_COPTS,
visibility = visibility,
)
@@ -74,14 +79,17 @@
native.genrule(
name = name + "_emit_verilog",
srcs = [],
- outs = [module_name + ".v"],
- cmd = "./$(location " + gen_binary_name + ") --target-dir $(RULEDIR)",
- tools = [":{}".format(gen_binary_name)],
+ outs = [module_name + ".sv"],
+ cmd = "PATH=$$(dirname $(execpath @kelvin_hw//third_party/llvm-firtool:firtool)):$$PATH ./$(location " + gen_binary_name + ") --target-dir $(RULEDIR)",
+ tools = [
+ ":{}".format(gen_binary_name),
+ "@kelvin_hw//third_party/llvm-firtool:firtool",
+ ],
)
verilog_library(
name = name + "_verilog",
- srcs = [module_name + ".v"],
+ srcs = [module_name + ".sv"],
deps = verilog_deps,
)
diff --git a/rules/deps.bzl b/rules/deps.bzl
index 917c021..73167c0 100644
--- a/rules/deps.bzl
+++ b/rules/deps.bzl
@@ -35,6 +35,14 @@
def kelvin_chisel_deps():
"""Dependent repositories to build chisel"""
+ # scala-reflect
+ scala_maven_import_external(
+ name = "org_scala_lang_scala_reflect",
+ artifact = "org.scala-lang:scala-reflect:%s" % "2.13.11",
+ server_urls = default_maven_server_urls(),
+ licenses = ["notice"],
+ )
+
# paranamer
scala_maven_import_external(
name = "com_thoughtworks_paranamer",
@@ -46,25 +54,25 @@
# json4s
scala_maven_import_external(
name = "org_json4s_json4s_ast",
- artifact = "org.json4s:json4s-ast_2.13:%s" % "3.6.12",
+ artifact = "org.json4s:json4s-ast_2.13:%s" % "4.0.6",
server_urls = default_maven_server_urls(),
licenses = ["notice"],
)
scala_maven_import_external(
name = "org_json4s_json4s_scalap",
- artifact = "org.json4s:json4s-scalap_2.13:%s" % "3.6.12",
+ artifact = "org.json4s:json4s-scalap_2.13:%s" % "4.0.6",
server_urls = default_maven_server_urls(),
licenses = ["notice"],
)
scala_maven_import_external(
name = "org_json4s_json4s_core",
- artifact = "org.json4s:json4s-core_2.13:%s" % "3.6.12",
+ artifact = "org.json4s:json4s-core_2.13:%s" % "4.0.6",
server_urls = default_maven_server_urls(),
licenses = ["notice"],
)
scala_maven_import_external(
name = "org_json4s_json4s_native",
- artifact = "org.json4s:json4s-native_2.13:%s" % "3.6.12",
+ artifact = "org.json4s:json4s-native_2.13:%s" % "4.0.6",
server_urls = default_maven_server_urls(),
licenses = ["notice"],
)
@@ -78,7 +86,7 @@
)
scala_maven_import_external(
name = "org_apache_commons_commons_text",
- artifact = "org.apache.commons:commons-text:%s" % "1.9",
+ artifact = "org.apache.commons:commons-text:%s" % "1.10.0",
server_urls = default_maven_server_urls(),
licenses = ["notice"],
)
@@ -99,36 +107,48 @@
licenses = ["notice"],
)
- # FIRRTL
+ # data-class
scala_maven_import_external(
- name = "edu_berkeley_cs_firrtl",
- artifact = "edu.berkeley.cs:firrtl_2.13:%s" % "1.5.1",
+ name = "io_github_alexarchambault_data_class",
+ artifact = "io.github.alexarchambault:data-class_2.13:%s" % "0.2.5",
+ server_urls = default_maven_server_urls(),
+ licenses = ["notice"],
+ )
+
+ # os-lib
+ scala_maven_import_external(
+ name = "com_lihaoyi_os_lib",
+ artifact = "com.lihaoyi:os-lib_2.13:%s" % "0.8.1",
+ server_urls = default_maven_server_urls(),
+ licenses = ["notice"],
+ )
+
+ # geny
+ scala_maven_import_external(
+ name = "com_lihaoyi_geny",
+ artifact = "com.lihaoyi:geny_2.13:%s" % "0.7.1",
+ server_urls = default_maven_server_urls(),
+ licenses = ["notice"],
+ )
+
+ # upickle
+ scala_maven_import_external(
+ name = "com_lihaoyi_upickle",
+ artifact = "com.lihaoyi:upickle_2.13:%s" % "2.0.0",
server_urls = default_maven_server_urls(),
licenses = ["notice"],
)
# Chisel3
scala_maven_import_external(
- name = "edu_berkeley_cs_chisel3",
- artifact = "edu.berkeley.cs:chisel3_2.13:%s" % "3.5.1",
+ name = "org_chipsalliance_chisel",
+ artifact = "org.chipsalliance:chisel_2.13:%s" % "5.1.0",
server_urls = default_maven_server_urls(),
licenses = ["notice"],
)
scala_maven_import_external(
- name = "edu_berkeley_cs_chisel3_core",
- artifact = "edu.berkeley.cs:chisel3-core_2.13:%s" % "3.5.1",
- server_urls = default_maven_server_urls(),
- licenses = ["notice"],
- )
- scala_maven_import_external(
- name = "edu_berkeley_cs_chisel3_macros",
- artifact = "edu.berkeley.cs:chisel3-macros_2.13:%s" % "3.5.1",
- server_urls = default_maven_server_urls(),
- licenses = ["notice"],
- )
- scala_maven_import_external(
- name = "edu_berkeley_cs_chisel3_plugin",
- artifact = "edu.berkeley.cs:chisel3-plugin_2.13.6:%s" % "3.5.1",
+ name = "org_chipsalliance_chisel_plugin",
+ artifact = "org.chipsalliance:chisel-plugin_2.13.6:%s" % "5.1.0",
server_urls = default_maven_server_urls(),
licenses = ["notice"],
)
diff --git a/rules/repos.bzl b/rules/repos.bzl
index a7bec48..b6e8e55 100644
--- a/rules/repos.bzl
+++ b/rules/repos.bzl
@@ -38,15 +38,15 @@
"@kelvin_hw//external:0001-Update-version-of-Googletest-for-bazel-compatitibili.patch",
"@kelvin_hw//external:0002-SystemC-support-for-verilator.patch",
"@kelvin_hw//external:0003-Add-systemc-lib-support.patch",
- "@kelvin_hw//external:0004-Build-verilator-v4.210.patch",
+ "@kelvin_hw//external:0004-Build-verilator-v4.226.patch",
],
)
# See https://github.com/bazelbuild/rules_scala/releases for up to date version information.
- rules_scala_version = "c711b4d1f0d1cc386c63ef748c9df14d2f3a187e"
+ rules_scala_version = "73719cbf88134d5c505daf6c913fe4baefd46917"
http_archive(
name = "io_bazel_rules_scala",
- sha256 = "556677f505634da64efc41912d280895e61f5da109d82bdee41cde4120a190a1",
+ sha256 = "48124dfd3387c72fd13d3d954b246a5c34eb83646c0c04a727c9a1ba98e876a6",
strip_prefix = "rules_scala-%s" % rules_scala_version,
type = "zip",
url = "https://github.com/bazelbuild/rules_scala/archive/%s.zip" % rules_scala_version,
@@ -65,3 +65,18 @@
strip_prefix = "abseil-cpp-20230125.0",
urls = ["https://github.com/abseil/abseil-cpp/archive/refs/tags/20230125.0.tar.gz"],
)
+
+ http_archive(
+ name = "glibc-2.37",
+ sha256 = "811f19f9200118ff94ede28a6e12307584152cdcbf3d366cd729ea2f855db255",
+ strip_prefix = "glibc-2.37",
+ urls = ["https://ftp.gnu.org/gnu/glibc/glibc-2.37.tar.gz"],
+ build_file = "@kelvin_hw//third_party/glibc-2.37:BUILD.bazel",
+ )
+
+ http_archive(
+ name = "llvm_firtool",
+ sha256 = "d22a894f2f8652b6c26e1d2a66551a7f015ce46e48f2bcdd785b01b9c8739277",
+ urls = ["https://repo1.maven.org/maven2/org/chipsalliance/llvm-firtool/1.52.0/llvm-firtool-1.52.0.jar"],
+ build_file = "@kelvin_hw//third_party/llvm-firtool:BUILD.bazel",
+ )
diff --git a/third_party/glibc-2.37/BUILD b/third_party/glibc-2.37/BUILD
new file mode 100644
index 0000000..e69de29
--- /dev/null
+++ b/third_party/glibc-2.37/BUILD
diff --git a/third_party/glibc-2.37/BUILD.bazel b/third_party/glibc-2.37/BUILD.bazel
new file mode 100644
index 0000000..28d873c
--- /dev/null
+++ b/third_party/glibc-2.37/BUILD.bazel
@@ -0,0 +1,40 @@
+load("@rules_foreign_cc//foreign_cc:defs.bzl", "configure_make")
+
+package(default_visibility = ["//visibility:public"])
+
+filegroup(
+ name = "all_srcs",
+ srcs = glob(["**"]),
+)
+
+configure_make(
+ name = "glibc-2.37",
+ args = ["-j"],
+ copts = [
+ "-O2",
+ ],
+ lib_source = "@glibc-2.37//:all_srcs",
+ out_shared_libs = [
+ "ld-linux-x86-64.so.2",
+ "libanl.so.1",
+ "libBrokenLocale.so.1",
+ "libc_malloc_debug.so.0",
+ "libcrypt.so.1",
+ "libc.so.6",
+ "libdl.so.2",
+ "libm.so.6",
+ "libmvec.so.1",
+ "libnsl.so.1",
+ "libnss_compat.so.2",
+ "libnss_db.so.2",
+ "libnss_dns.so.2",
+ "libnss_files.so.2",
+ "libnss_hesiod.so.2",
+ "libpthread.so.0",
+ "libresolv.so.2",
+ "librt.so.1",
+ "libthread_db.so.1",
+ "libutil.so.1",
+ ],
+ targets = ["all", "install"],
+)
\ No newline at end of file
diff --git a/third_party/llvm-firtool/BUILD b/third_party/llvm-firtool/BUILD
new file mode 100644
index 0000000..6d5e14b
--- /dev/null
+++ b/third_party/llvm-firtool/BUILD
@@ -0,0 +1,13 @@
+# Copyright 2024 Google LLC
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
diff --git a/third_party/llvm-firtool/BUILD.bazel b/third_party/llvm-firtool/BUILD.bazel
new file mode 100644
index 0000000..efc601a
--- /dev/null
+++ b/third_party/llvm-firtool/BUILD.bazel
@@ -0,0 +1,26 @@
+# Copyright 2024 Google LLC
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+
+exports_files(glob(["org.chipsalliance/llvm-firtool/linux-x64/bin/**"]))
+
+package(default_visibility = ["//visibility:public"])
+
+sh_binary(
+ name = "firtool",
+ srcs = [":firtool.sh"],
+ data = [
+ "@llvm_firtool//:org.chipsalliance/llvm-firtool/linux-x64/bin/firtool",
+ "@glibc-2.37//:glibc-2.37",
+ ]
+)
diff --git a/third_party/llvm-firtool/firtool.sh b/third_party/llvm-firtool/firtool.sh
new file mode 100755
index 0000000..1d5bfed
--- /dev/null
+++ b/third_party/llvm-firtool/firtool.sh
@@ -0,0 +1,14 @@
+#!/bin/bash
+
+SCRIPT_DIR="$(dirname "$BASH_SOURCE")"
+RUNFILES_DIR=$SCRIPT_DIR/firtool.runfiles
+
+# ./bazel-out/k8-opt-exec-2B5CBBC6/bin/third_party/llvm-firtool/firtool.runfiles/kelvin_hw/third_party/llvm-firtool/firtool
+# ./bazel-out/k8-opt-exec-2B5CBBC6/bin/third_party/llvm-firtool/firtool.runfiles/llvm_firtool/org.chipsalliance/llvm-firtool/linux-x64/bin/firtool
+# ./bazel-out/k8-opt-exec-2B5CBBC6/bin/third_party/llvm-firtool/firtool.runfiles/glibc-2.37/glibc-2.37/lib/ld-linux-x86-64.so.2
+
+LD_SO=${RUNFILES_DIR}/glibc-2.37/glibc-2.37/lib/ld-linux-x86-64.so.2
+LIB_PATH=${RUNFILES_DIR}/glibc-2.37/glibc-2.37/lib:/usr/lib/x86_64-linux-gnu:/usr/lib64:/usr/lib
+
+${LD_SO} --library-path ${LIB_PATH} ${RUNFILES_DIR}/llvm_firtool/org.chipsalliance/llvm-firtool/linux-x64/bin/firtool $*
+exit $?
\ No newline at end of file
