Plumb rvv_idle output RvvCore.
Change-Id: I6252637a06289e23027e4be4fd12dea5156c9a76
diff --git a/hdl/chisel/src/kelvin/rvv/RvvCore.scala b/hdl/chisel/src/kelvin/rvv/RvvCore.scala
index 36d1976..4e57b99 100644
--- a/hdl/chisel/src/kelvin/rvv/RvvCore.scala
+++ b/hdl/chisel/src/kelvin/rvv/RvvCore.scala
@@ -111,6 +111,7 @@
| output [1:0] configXrm,
| output [2:0] configSew,
| output [2:0] configLmul,
+ | output logic rvv_idle,
|""".stripMargin.replaceAll("VSTART_LEN", (log2Ceil(vlen) - 1).toString)
@@ -254,7 +255,8 @@
| .vector_csr(vector_csr),
| .vcsr_ready(vcsr_ready),
| .config_state_valid(configStateValid),
- | .config_state(config_state)
+ | .config_state(config_state),
+ | .rvv_idle(rvv_idle)
|""".stripMargin.replaceAll("GENN", instructionLanes.toString)
coreInstantiation += " );\n"
@@ -318,6 +320,7 @@
val configXrm = Output(UInt(2.W))
val configSew = Output(UInt(3.W))
val configLmul = Output(UInt(3.W))
+ val rvv_idle = Output(Bool())
})
// Resources must be sorted topologically by dependency DAG
@@ -413,6 +416,7 @@
io.configState.bits.xrm := rvvCoreWrapper.io.configXrm
io.configState.bits.sew := rvvCoreWrapper.io.configSew
io.configState.bits.lmul := rvvCoreWrapper.io.configLmul
+ io.rvv_idle := rvvCoreWrapper.io.rvv_idle
vstart := Mux(rvvCoreWrapper.io.vcsr_valid, rvvCoreWrapper.io.vcsr_vstart, vstart)
vxrm := Mux(rvvCoreWrapper.io.vcsr_valid, rvvCoreWrapper.io.vcsr_xrm, vxrm)
diff --git a/hdl/chisel/src/kelvin/rvv/RvvInterface.scala b/hdl/chisel/src/kelvin/rvv/RvvInterface.scala
index e6346a6..139de23 100644
--- a/hdl/chisel/src/kelvin/rvv/RvvInterface.scala
+++ b/hdl/chisel/src/kelvin/rvv/RvvInterface.scala
@@ -63,4 +63,6 @@
// Async scalar regfile writes.
val async_rd = Decoupled(new RegfileWriteDataIO)
+
+ val rvv_idle = Output(Bool())
}
\ No newline at end of file
diff --git a/hdl/chisel/src/kelvin/scalar/Decode.scala b/hdl/chisel/src/kelvin/scalar/Decode.scala
index 1cda259..8b0715d 100644
--- a/hdl/chisel/src/kelvin/scalar/Decode.scala
+++ b/hdl/chisel/src/kelvin/scalar/Decode.scala
@@ -295,6 +295,7 @@
val rvv = Option.when(p.enableRvv)(
Vec(p.instructionLanes, Decoupled(new RvvCompressedInstruction)))
val rvvState = Option.when(p.enableRvv)(Input(Valid(new RvvConfigState(p))))
+ val rvvIdle = Option.when(p.enableRvv)(Input(Bool()))
// Vector interface, to maintain interface compatibility with old dispatch
// unit.
@@ -450,12 +451,11 @@
// Evaluate whether the core is idle.
// The general method of operation is to check that
// scoreboards for register files are clear, and no LSU operation is active.
- // TODO(atv): Extend this to consider vector operations.
val coreIdle =
(
(io.scoreboard.regd === 0.U) &&
(io.fscoreboard.getOrElse(0.U) === 0.U) &&
- // /* vec scoreboard clear */ &&
+ io.rvvIdle.getOrElse(true.B) &&
!io.lsuActive
)
diff --git a/hdl/chisel/src/kelvin/scalar/SCore.scala b/hdl/chisel/src/kelvin/scalar/SCore.scala
index 1e37aa6..8905f2f 100644
--- a/hdl/chisel/src/kelvin/scalar/SCore.scala
+++ b/hdl/chisel/src/kelvin/scalar/SCore.scala
@@ -421,6 +421,7 @@
// Connect dispatch
dispatch.io.rvv.get <> io.rvvcore.get.inst
dispatch.io.rvvState.get := io.rvvcore.get.configState
+ dispatch.io.rvvIdle.get := io.rvvcore.get.rvv_idle
// Register inputs
io.rvvcore.get.rs := regfile.io.readData
diff --git a/hdl/verilog/rvv/design/RvvCore.sv b/hdl/verilog/rvv/design/RvvCore.sv
index ecda31b..d1b9c8b 100644
--- a/hdl/verilog/rvv/design/RvvCore.sv
+++ b/hdl/verilog/rvv/design/RvvCore.sv
@@ -73,7 +73,10 @@
// Config state
output config_state_valid,
- output RVVConfigState config_state
+ output RVVConfigState config_state,
+
+ // Idle
+ output logic rvv_idle
);
logic [N-1:0] frontend_cmd_valid;
RVVCmd [N-1:0] frontend_cmd_data;
@@ -180,7 +183,6 @@
trap_valid_rvs2rvv = 0;
end
- logic rvv_idle;
logic [`ISSUE_LANE-1:0] insts_ready_cq2rvs;
rvv_backend backend(
.clk(clk),
