| commit | 2b02fc5bae49ee3af84af61bc46d90a38178c4bc | [log] [tgz] |
|---|---|---|
| author | tianyu.li <tianyu.li@verisilicon.com> | Thu Jan 16 21:01:53 2025 +0800 |
| committer | Derek Chow <derekjchow@google.com> | Mon Jan 27 10:02:57 2025 -0800 |
| tree | d9a7d3a544d1b8f0d5412ab901321da0f56fe1d0 | |
| parent | edc203eca6cb4df48c6660ca39d6da942648d61f [diff] |
1. fix ari decoder for immediate data; 2. fix decoder ctrl; 3. fix addsub and shifter sturate logic; 4. optimize viota instruction for better timing; 5. Double Reservation station depth. Change-Id: Ic381343f4316c0f79db4533219c52836718a3b93
Kelvin is a RISC-V32IM core with a custom instruction set.
More information on the design can be found in the overview.
Kelvin uses bazel as it's build system. The Verilated simulator for Kelvin can be generated using:
bazel build //tests/verilator_sim:core_sim
The verilog source for the Kelvin core can be generated using:
bazel build //hdl/chisel/src/kelvin:core_cc_library_emit_verilog
Verilog source for the Matcha SoC can be generated using:
bazel clean --expunge # To generate the ToT sha bazel build //hdl/chisel:matcha_kelvin_verilog