| commit | 6edcd4e5a3f1bba747833970daf821a54c573fd1 | [log] [tgz] |
|---|---|---|
| author | Alex Van Damme <atv@google.com> | Tue Aug 19 13:31:45 2025 -0700 |
| committer | Alex Van Damme <atv@google.com> | Thu Aug 28 17:16:21 2025 -0700 |
| tree | df6c375c3259669b31a287455047a52f92505056 | |
| parent | 0004fc32c1b0d4287693d1d0d1febce780730cf0 [diff] |
refactor(fpga): Replace tlgen xbar with Chisel-based KelvinXbar This commit replaces the legacy `tlgen`-based crossbar with the new, data-driven Chisel-based `KelvinXbar` in the FPGA design. This change simplifies the build system, improves maintainability, and provides a more flexible and robust interconnect. Key changes: - Removed the `tlgen` and `post_process_xbar.py` infrastructure from the FPGA build system. - Instantiated the new `KelvinXbar` in `kelvin_soc.sv`, replacing the old crossbar and all associated width-sizers. - Updated the clocking and reset logic to support the new crossbar's asynchronous domains, placing the Ibex core on its own clock. - Removed the now-redundant Verilog implementations of the TileLink-UL primitives (FIFOs, sockets, width bridges). - Added integrity generation to the `CoreTlul` module to ensure data integrity on the TileLink bus. - Increased the FPGA clock frequency to 80MHz. Change-Id: I340658419ca5cc93acee481c16334aeb026b2e7e
Kelvin is a RISC-V32IM core with a custom instruction set.
More information on the design can be found in the overview.
Kelvin uses bazel as it's build system. The Verilated simulator for Kelvin can be generated using:
bazel build //tests/verilator_sim:core_sim
The verilog source for the Kelvin core can be generated using:
bazel build //hdl/chisel/src/kelvin:core_cc_library_emit_verilog
Verilog source for the Matcha SoC can be generated using:
bazel clean --expunge # To generate the ToT sha bazel build //hdl/chisel:matcha_kelvin_verilog