| commit | 2133ce96fda9c7f7ee33c053a38db4f370f0bf03 | [log] [tgz] |
|---|---|---|
| author | Alex Van Damme <atv@google.com> | Tue Sep 09 10:15:17 2025 -0700 |
| committer | Alex Van Damme <atv@google.com> | Tue Sep 09 12:26:11 2025 -0700 |
| tree | 32f3b47e4a6876ee283138b171c78ce7f33d73c2 | |
| parent | d79c4a7b1535787d4b002fc8b8a2412b7744da39 [diff] |
feat(spi): Add packed write transaction support This change introduces a "packed" write transaction to the SPI master, allowing for a full TileLink write transaction to be sent in a single, uninterrupted SPI burst. This significantly improves performance for loading data to the device. The following changes are included: - A `packed_write_transaction` method has been added to the `SPIMaster` in `kelvin_test_utils/spi_master.py`. - A new test case, `test_packed_write_transaction`, has been added to `tests/cocotb/tlul/test_spi_to_tlul.py` to validate the new functionality. - The `poll_reg_for_value` method in `SPIMaster` has been refactored to correctly handle the pipelined nature of SPI reads, which was discovered during the development of the packed write feature. Change-Id: I1703af4d083dc75781550a38c43ac726a40cfb43
Kelvin is a RISC-V32IM core with a custom instruction set.
More information on the design can be found in the overview.
Kelvin uses bazel as it's build system. The Verilated simulator for Kelvin can be generated using:
bazel build //tests/verilator_sim:core_sim
The verilog source for the Kelvin core can be generated using:
bazel build //hdl/chisel/src/kelvin:core_cc_library_emit_verilog
Verilog source for the Matcha SoC can be generated using:
bazel clean --expunge # To generate the ToT sha bazel build //hdl/chisel:matcha_kelvin_verilog