Fix load segment2 m2 test cases - set vl correctly - fix expected output pattern Because the impl is currently incorrect, the changed test cases now fail, and are temporarily marked as skipped before we have the fixes. Change-Id: Ibee12af3d6ae1eca16f59edfa2cc9aa9a1d4a13b
Kelvin is a RISC-V32IM core with a custom instruction set.
More information on the design can be found in the overview.
Kelvin uses bazel as it's build system. The Verilated simulator for Kelvin can be generated using:
bazel build //tests/verilator_sim:core_sim
The verilog source for the Kelvin core can be generated using:
bazel build //hdl/chisel/src/kelvin:core_cc_library_emit_verilog
Verilog source for the Matcha SoC can be generated using:
bazel clean --expunge # To generate the ToT sha bazel build //hdl/chisel:matcha_kelvin_verilog