1. Add VRF struct in rvv.svh 2. Add some define in rvv_define.svh
Change-Id: I51cb4b5a84224d1dc83a8ff0098ac1b769ee6724
diff --git a/hdl/verilog/rvv/design/rvv.svh b/hdl/verilog/rvv/design/rvv.svh
index d4c36b9..296b328 100755
--- a/hdl/verilog/rvv/design/rvv.svh
+++ b/hdl/verilog/rvv/design/rvv.svh
@@ -4,16 +4,16 @@
// IF stage, RVS to Command Queue
//
typedef struct packed {
- logic [`VTYPE_VILL-1:0] vill, // 0:not illegal, 1:illegal
- logic [`VTYPE_VMA-1:0] vma, // 0:inactive element undisturbed, 1:inactive element agnostic
- logic [`VTYPE_VTA-1:0] vta, // 0:tail undisturbed, 1:tail agnostic
- logic [`VTYPE_VSEW-1:0] vsew, // support: 000:SEW8, 001:SEW16, 010:SEW32
- logic [`VTYPE_VLMUL-1:0] vlmul // support: 110:LMUL1/4, 111:LMUL1/2, 000:LMUL1, 001:LMUL2, 010:LMUL4, 011:LMUL8
+ logic [`VTYPE_VILL_WIDTH-1:0] vill, // 0:not illegal, 1:illegal
+ logic [`VTYPE_VMA_WIDTH-1:0] vma, // 0:inactive element undisturbed, 1:inactive element agnostic
+ logic [`VTYPE_VTA_WIDTH-1:0] vta, // 0:tail undisturbed, 1:tail agnostic
+ logic [`VTYPE_VSEW_WIDTH-1:0] vsew, // support: 000:SEW8, 001:SEW16, 010:SEW32
+ logic [`VTYPE_VLMUL_WIDTH-1:0] vlmul // support: 110:LMUL1/4, 111:LMUL1/2, 000:LMUL1, 001:LMUL2, 010:LMUL4, 011:LMUL8
} VTYPE_t;
typedef struct packed {
- logic [`VCSR_VXRM-1:0] vxrm,
- logic [`VCSR_VXSAT-1:0] vxsat
+ logic [`VCSR_VXRM_WIDTH-1:0] vxrm,
+ logic [`VCSR_VXSAT_WIDTH-1:0] vxsat
} VCSR_t;
typedef struct packed {
@@ -36,8 +36,7 @@
// It is used to distinguish which execute units that VVV/VVX/VX uop is dispatch to, based on inst_encoding[6:0]
typedef enum logic [2:0] {
ALU,
- PMT,
- RDT,
+ PMTRDT,
MUL,
MAC,
LSU
@@ -229,10 +228,10 @@
// uop classification used for dispatch rule
typedef enum logic [1:0] {
- VVV, // this uop will use 2 read ports of VRF
- VVX, // this uop will use 1 read ports of VRF
- VX, // this uop will use 0 read ports of VRF
- MACV // this uop will use 3 read ports of VRF
+ VV, // this uop will use 2 read ports of VRF
+ VX, // this uop will use 1 read ports of VRF
+ X, // this uop will use 0 read ports of VRF
+ VVV // this uop will use 3 read ports of VRF
} UOP_CLASS_e;
// Effective Element Width
@@ -274,6 +273,31 @@
//
// DP stage,
//
+// VRF struct
+typedef struct packed {
+ logic dp2vrf_vr0_valid;
+ logic [`REGFILE_INDEX_WIDTH-1:0] dp2vrf_vr0_addr;
+ logic dp2vrf_vr1_valid;
+ logic [`REGFILE_INDEX_WIDTH-1:0] dp2vrf_vr1_addr;
+ logic dp2vrf_vr2_valid;
+ logic [`REGFILE_INDEX_WIDTH-1:0] dp2vrf_vr2_addr;
+ logic dp2vrf_vr3_valid;
+ logic [`REGFILE_INDEX_WIDTH-1:0] dp2vrf_vr3_addr;
+}DP2VRF_t;
+
+typedef struct packed {
+ logic vrf2mux_rd0_valid;
+ logic [`VLEN-1:0] vrf2mux_rd0_data;
+ logic vrf2mux_rd1_valid;
+ logic [`VLEN-1:0] vrf2mux_rd1_data;
+ logic vrf2mux_rd2_valid;
+ logic [`VLEN-1:0] vrf2mux_rd2_data;
+ logic vrf2mux_rd3_valid;
+ logic [`VLEN-1:0] vrf2mux_rd3_data;
+ logic vrf2mux_v0_valid;
+ logic [`VLEN-1:0] vrf2mux_v0_data;
+}VRF2MUX_t;
+
// specify whether the current byte belongs to 'prestart' or 'body-inactive' or 'body-active' or 'tail'
typedef enum logic [1:0] {
NOT_CHANGE, // the byte is not changed, which may belong to 'prestart' or superfluous element in widening/narrowing uop
diff --git a/hdl/verilog/rvv/design/rvv_define.svh b/hdl/verilog/rvv/design/rvv_define.svh
index d1271d3..be8d93b 100755
--- a/hdl/verilog/rvv/design/rvv_define.svh
+++ b/hdl/verilog/rvv/design/rvv_define.svh
@@ -1,11 +1,12 @@
// number of scalar core issue lane
`define ISSUE_LANE 4
-// the max number of instructions are decoded per cycle in ID stage
+
+// the max number of instructions are decoded per cycle in DE stage
`define NUM_DE_INST 2
+
// the max number of uops are dispated per cycle in DP stage
`define NUM_DP_UOP 2
-//
-`define NUM_DP_RS
+
// the max number of uops are retired per cycle in WB stage
`define NUM_WB_UOP 4
@@ -18,22 +19,26 @@
`define INST_WIDTH 27
`define XLEN 32
`define REGFILE_INDEX_WIDTH 5
-// an instruction will be split to EMUL_max=8 uops at most, so UOP_INDEX_WITH is log2(8).
-`define UOP_INDEX_WIDTH 3
+
+// an instruction will be split to EMUL_max=8 uops at most
+`define EMUL_MAX 8
+`define UOP_INDEX_WIDTH $clog2(`EMUL_MAX)
// Vector CSR
`define VLEN 128
`define VLENB `VLEN/8
+
// vstart <= VLMAX_max and vl <= VLMAX_max, VLMAX_max=VLEN*LMUL_max/SEW_min=128
`define VSTART_WIDTH $clog2(`VLEN)+1
`define VL_WIDTH $clog2(`VLEN)+1
-`define VTYPE_VILL 1
-`define VTYPE_VMA 1
-`define VTYPE_VTA 1
-`define VTYPE_VSEW 3
-`define VTYPE_VLMUL 3
-`define VCSR_VXRM 2
-`define VCSR_VXSAT 1
+`define VTYPE_VILL_WIDTH 1
+`define VTYPE_VMA_WIDTH 1
+`define VTYPE_VTA_WIDTH 1
+`define VTYPE_VSEW_WIDTH 3
+`define VTYPE_VLMUL_WIDTH 3
+`define VCSR_VXRM_WIDTH 2
+`define VCSR_VXSAT_WIDTH 1
+
// Instruction encoding
`define FUNCT6_WIDTH 6
`define VM_WIDTH 1
@@ -45,6 +50,24 @@
`define VD_WIDTH 5
`define RD_WIDTH 5
`define OPCODE_WIDTH 7
+
+// vtype.vlmul
+`define LMUL1_4 3'b110
+`define LMUL1_2 3'b111
+`define LMUL1 3'b000
+`define LMUL2 3'b001
+`define LMUL4 3'b010
+`define LMUL8 3'b011
+
+// vtype.vsew
+`define SEW8 3'b000
+`define SEW16 3'b001
+`define SEW32 3'b010
+
+// instruction opcode
+`define OPCODE_LOAD 2'b00
+`define OPCODE_STORE 2'b01
+`define OPCODE_ARITH 2'b00
// Reservation Station data width
`define ALU_RS_WIDTH $bits(ALU_RS_t)
