commit | 1561552b7494b62189413b3a2f8f8427c02c9643 | [log] [tgz] |
---|---|---|
author | Derek Chow <derekjchow@google.com> | Mon Jul 28 14:00:45 2025 -0700 |
committer | Derek Chow <derekjchow@google.com> | Tue Jul 29 13:45:33 2025 -0700 |
tree | dab4de67c8cb6e9a7594a97f92571cf1b01d342a | |
parent | 8cd3a3a8969adbcce9efad0ced2d3b51b9588b1f [diff] |
Allow LSU to accept multiple instructions in one cycle. Change-Id: I6ff3d6e795182bcd921c40e24bce6af4aeda4e77
Kelvin is a RISC-V32IM core with a custom instruction set.
More information on the design can be found in the overview.
Kelvin uses bazel as it's build system. The Verilated simulator for Kelvin can be generated using:
bazel build //tests/verilator_sim:core_sim
The verilog source for the Kelvin core can be generated using:
bazel build //hdl/chisel/src/kelvin:core_cc_library_emit_verilog
Verilog source for the Matcha SoC can be generated using:
bazel clean --expunge # To generate the ToT sha bazel build //hdl/chisel:matcha_kelvin_verilog