feat(hdl): Add rocket-chip AsyncQueue and smoke test This commit introduces the `AsyncQueue` from the `chipsalliance/rocket-chip` library to handle asynchronous clock domain crossings. The key changes are: - Added `rocket-chip` and `diplomacy` as external dependencies. - Created a `chisel_library` for the `AsyncQueue` module and its dependencies from `rocket-chip`. - Added `AsyncQueueSmokeTest.scala`, a ChiselSim-based smoke test that verifies the functionality of the `AsyncQueue` by passing a value between two different clock domains. The test also enables VCD waveform dumping for easier debugging. - Updated the `chisel_library` Bazel rule to allow suppressing fatal warnings, which was necessary for the `rocket-chip` library. This provides a robust and tested solution for handling asynchronous FIFOs in the Chisel design. Change-Id: I53ee24a52852ebd49f27a3e2f6792b88a828f978
Kelvin is a RISC-V32IM core with a custom instruction set.
More information on the design can be found in the overview.
Kelvin uses bazel as it's build system. The Verilated simulator for Kelvin can be generated using:
bazel build //tests/verilator_sim:core_sim
The verilog source for the Kelvin core can be generated using:
bazel build //hdl/chisel/src/kelvin:core_cc_library_emit_verilog
Verilog source for the Matcha SoC can be generated using:
bazel clean --expunge # To generate the ToT sha bazel build //hdl/chisel:matcha_kelvin_verilog