Fix: Prevent X-propagation in debug module
The data0 and cmderr registers in the debug module were not being
reset by the global reset, only by the dmactive signal. This could
lead to X-propagation if the registers were read before being
written to.
This change ensures that these registers are reset to 0 when dmactive
is false.
Change-Id: I35d37ed21a15b0b2e67139dc1591c787256c0737
diff --git a/hdl/chisel/src/kelvin/scalar/Debug.scala b/hdl/chisel/src/kelvin/scalar/Debug.scala
index 3e5130f..4b683cf 100644
--- a/hdl/chisel/src/kelvin/scalar/Debug.scala
+++ b/hdl/chisel/src/kelvin/scalar/Debug.scala
@@ -93,8 +93,8 @@
val dmcontrol = RegInit(1.U(32.W))
val dmactive = dmcontrol(0)
- val data0 = withReset(!dmactive) { RegInit(0.U(32.W)) }
- val cmderr = withReset(!dmactive) { RegInit(0.U(3.W)) }
+ val data0 = RegInit(0.U(32.W))
+ val cmderr = RegInit(0.U(32.W))
val dmcontrol_wvalid = (req.fire && req.bits.isAddrDmcontrol && req.bits.isWrite)
for (i <- 0 until nHart) {
@@ -172,6 +172,7 @@
cmderr := MuxCase(cmderr, Seq(
abstractcs_wvalid -> (cmderr & ~(req.bits.data(10,8))), // cmderr is W1C
(abstractCmdValid && !io.halted(0)) -> 4.U(3.W),
+ !dmactive -> 0.U(3.W),
))
val busy = abstractCmdValid && !abstractCmdComplete
val abstractcs = Wire(UInt(32.W))
@@ -206,6 +207,7 @@
(io.halted(0) && req.valid && !req.bits.write && regnoIsCsr && io.csr_rd.valid) -> io.csr_rd.bits,
(io.halted(0) && req.valid && !req.bits.write && regnoIsScalar) -> io.scalar_rs.data,
(io.halted(0) && req.valid && !req.bits.write && regnoIsFloat) -> io.float_rs.map(_.data).getOrElse(Fp32.Zero(false.B)).asWord,
+ !dmactive -> 0.U(32.W),
))
val rsp = req.map(reqBits => {
