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opensecura / hw / kelvin / 56decb04fac9fd450141b2e096facd09b6ada06d
commit56decb04fac9fd450141b2e096facd09b6ada06d[log] [tgz]
authorDavid Gao <davidgao@google.com>Fri Sep 12 22:52:14 2025 +0000
committerDavid Gao <davidgao@google.com>Fri Sep 12 18:42:17 2025 -0700
treebe9e0e3734892ba905ebdcce5af93b3f8b25a754
parentc775ee31c0ef80ea79e04f3cfadb91e999dd1157 [diff]
Switch from VLM to VLE in VCPOP tests

Atm our VLM is broken. Use VLE with reinterpret for VCPOP tests.
Dedicated VLM/VSM tests will be added later.

Added fractional byte support so we can test VCPOP more thouroughly.

Change-Id: I531270db1fe23d380903fb96c4c8772cecf850b6
2 files changed
tree: be9e0e3734892ba905ebdcce5af93b3f8b25a754
  1. doc/
  2. examples/
  3. external/
  4. fpga/
  5. hdl/
  6. hw_sim/
  7. kelvin_test_utils/
  8. lib/
  9. platforms/
  10. rules/
  11. tests/
  12. third_party/
  13. toolchain/
  14. utils/
  15. .bazelrc
  16. .bazelversion
  17. .gitignore
  18. CONTRIBUTING.md
  19. LICENSE
  20. PREUPLOAD.cfg
  21. README.md
  22. WORKSPACE
README.md

Kelvin

Kelvin is a RISC-V32IM core with a custom instruction set.

Kelvin block diagram

More information on the design can be found in the overview.

Getting Started

  • If you are hardware engineer looking to integrate Kelvin into your design, check out our integration guide.
  • If you are a software engineer looking to write code for Kelvin, start with this tutorial.

Building

Kelvin uses bazel as it's build system. The Verilated simulator for Kelvin can be generated using:

bazel build //tests/verilator_sim:core_sim

The verilog source for the Kelvin core can be generated using:

bazel build //hdl/chisel/src/kelvin:core_cc_library_emit_verilog

Verilog source for the Matcha SoC can be generated using:

bazel clean --expunge  # To generate the ToT sha
bazel build //hdl/chisel:matcha_kelvin_verilog