| commit | 0d24fda4685001d413dbae3dded21aec4ab4a124 | [log] [tgz] |
|---|---|---|
| author | Tianyu Li <Tianyu.Li@verisilicon.com> | Tue Dec 17 10:44:28 2024 +0800 |
| committer | Derek Chow <derekjchow@google.com> | Mon Jan 13 16:40:43 2025 -0800 |
| tree | e53235e6b7d22c7af4dc9a2c9faf4056368dbd5f | |
| parent | 89078f0d1b9865f6780638b5ad34536da9bf5d18 [diff] |
Adjust type name based on new svh file Change-Id: I2b18f5fb557984cfd44a4bde7f20d3fced9d48e3
Kelvin is a RISC-V32IM core with a custom instruction set.
More information on the design can be found in the overview.
Kelvin uses bazel as it's build system. The Verilated simulator for Kelvin can be generated using:
bazel build //tests/verilator_sim:core_sim
The verilog source for the Kelvin core can be generated using:
bazel build //hdl/chisel/src/kelvin:core_cc_library_emit_verilog
Verilog source for the Matcha SoC can be generated using:
bazel clean --expunge # To generate the ToT sha bazel build //hdl/chisel:matcha_kelvin_verilog