| commit | 0a5012dac31defec46ced59c1a3110f93e40ec21 | [log] [tgz] |
|---|---|---|
| author | Alex Van Damme <atv@google.com> | Mon Mar 04 13:17:38 2024 -0800 |
| committer | Alex Van Damme <atv@google.com> | Mon Mar 04 13:59:08 2024 -0800 |
| tree | 7fc4b8b6f746685fdd323223cfec5db9f91fc7be | |
| parent | a098a65e1df1d427baec8b77045028a2e646fe30 [diff] |
Set cmdqDepth in VConvControl to instructionLanes - This lets the testbench pass on instructionLanes configurations other than 4. Change-Id: Ic5647aaa0c1cb38694ebaae8bfbea5365af515dc
Kelvin is a RISC-V32IM core with a custom instruction set.
More information on the design can be found in the overview.
Kelvin uses bazel as it's build system. The Verilated simulator for Kelvin can be generated using:
bazel build //tests/verilator_sim:core_sim
The verilog source for the Kelvin core can be generated using:
bazel build //hdl/chisel:core_cc_library_emit_verilog
Verilog source for the Matcha SoC can be generated using:
bazel clean --expunge # To generate the ToT sha bazel build //hdl/chisel:matcha_kelvin_verilog