Remove AXI WID signal
- WID is AXI3 only, we're AXI4.
Change-Id: I7aa6d3a8f1a071d89454f1a927e1e6fdc3013e28
diff --git a/hdl/chisel/src/bus/Axi.scala b/hdl/chisel/src/bus/Axi.scala
index 7a40960..c436341 100644
--- a/hdl/chisel/src/bus/Axi.scala
+++ b/hdl/chisel/src/bus/Axi.scala
@@ -47,7 +47,6 @@
// ARM IHI 0022E, A2.3
class AxiWriteData(dataWidthBits: Int, idBits: Int) extends Bundle {
// "Required"
- val id = UInt(idBits.W)
val data = UInt(dataWidthBits.W)
val last = Bool()
// "Optional"
diff --git a/hdl/chisel/src/kelvin/DBus2Axi.scala b/hdl/chisel/src/kelvin/DBus2Axi.scala
index 0a7f639..31fbfdd 100644
--- a/hdl/chisel/src/kelvin/DBus2Axi.scala
+++ b/hdl/chisel/src/kelvin/DBus2Axi.scala
@@ -66,7 +66,6 @@
io.axi.write.addr.bits.prot := 2.U
io.axi.write.data.valid := io.dbus.valid && io.dbus.write
- io.axi.write.data.bits.id := 0.U
io.axi.write.data.bits.strb := io.dbus.wmask
io.axi.write.data.bits.data := io.dbus.wdata
io.axi.write.data.bits.last := true.B
diff --git a/hdl/chisel/src/kelvin/L1DCache.scala b/hdl/chisel/src/kelvin/L1DCache.scala
index 1792236..8558f77 100644
--- a/hdl/chisel/src/kelvin/L1DCache.scala
+++ b/hdl/chisel/src/kelvin/L1DCache.scala
@@ -560,7 +560,6 @@
io.axi.write.resp.ready := true.B
io.axi.write.data.valid := axiwdatavalid
- io.axi.write.data.bits.id := 0.U
io.axi.write.data.bits.last := true.B
io.axi.write.data.bits.data := axiwdatabuf.asUInt
io.axi.write.data.bits.strb := axiwstrbbuf.asUInt
diff --git a/hdl/chisel/src/kelvin/vector/VSt.scala b/hdl/chisel/src/kelvin/vector/VSt.scala
index 0e7bf23..0107b27 100644
--- a/hdl/chisel/src/kelvin/vector/VSt.scala
+++ b/hdl/chisel/src/kelvin/vector/VSt.scala
@@ -79,7 +79,6 @@
io.axi.data.valid := false.B
io.axi.data.bits.strb := 0.U
io.axi.data.bits.data := 0.U
- io.axi.data.bits.id := 0.U
io.axi.data.bits.last := true.B
io.axi.resp.ready := false.B
diff --git a/tests/verilator_sim/kelvin/core_if.h b/tests/verilator_sim/kelvin/core_if.h
index ee2b563..b183f58 100644
--- a/tests/verilator_sim/kelvin/core_if.h
+++ b/tests/verilator_sim/kelvin/core_if.h
@@ -91,7 +91,6 @@
sc_in<bool> io_axi0_write_data_valid;
sc_in<sc_bv<KP_lsuDataBits> > io_axi0_write_data_bits_data;
sc_in<sc_bv<KP_lsuDataBits/8> > io_axi0_write_data_bits_strb;
- sc_in<sc_bv<6> > io_axi0_write_data_bits_id;
sc_in<bool> io_axi0_write_data_bits_last;
sc_in<bool> io_axi0_write_resp_ready;
sc_out<bool> io_axi0_write_resp_valid;
@@ -132,7 +131,6 @@
sc_in<bool> io_axi1_write_data_valid;
sc_in<sc_bv<KP_lsuDataBits> > io_axi1_write_data_bits_data;
sc_in<sc_bv<KP_lsuDataBits/8> > io_axi1_write_data_bits_strb;
- sc_in<sc_bv<6> > io_axi1_write_data_bits_id;
sc_in<bool> io_axi1_write_data_bits_last;
sc_in<bool> io_axi1_write_resp_ready;
sc_out<bool> io_axi1_write_resp_valid;
diff --git a/tests/verilator_sim/kelvin/core_tb.cc b/tests/verilator_sim/kelvin/core_tb.cc
index 5297172..dfcc4b2 100644
--- a/tests/verilator_sim/kelvin/core_tb.cc
+++ b/tests/verilator_sim/kelvin/core_tb.cc
@@ -128,7 +128,6 @@
sc_signal<bool> io_axi0_write_data_valid;
sc_signal<sc_bv<KP_lsuDataBits> > io_axi0_write_data_bits_data;
sc_signal<sc_bv<KP_lsuDataBits/8> > io_axi0_write_data_bits_strb;
- sc_signal<sc_bv<6> > io_axi0_write_data_bits_id;
sc_signal<bool> io_axi0_write_data_bits_last;
sc_signal<bool> io_axi0_write_resp_ready;
sc_signal<bool> io_axi0_write_resp_valid;
@@ -169,7 +168,6 @@
sc_signal<bool> io_axi1_write_data_valid;
sc_signal<sc_bv<KP_lsuDataBits> > io_axi1_write_data_bits_data;
sc_signal<sc_bv<KP_lsuDataBits/8> > io_axi1_write_data_bits_strb;
- sc_signal<sc_bv<6> > io_axi1_write_data_bits_id;
sc_signal<bool> io_axi1_write_data_bits_last;
sc_signal<bool> io_axi1_write_resp_ready;
sc_signal<bool> io_axi1_write_resp_valid;
@@ -314,7 +312,6 @@
BINDAXI(io_axi0_write_data_valid);
BINDAXI(io_axi0_write_data_bits_data);
BINDAXI(io_axi0_write_data_bits_strb);
- BINDAXI(io_axi0_write_data_bits_id);
BINDAXI(io_axi0_write_data_bits_last);
BINDAXI(io_axi0_write_resp_ready);
BINDAXI(io_axi0_write_resp_valid);
@@ -355,7 +352,6 @@
BINDAXI(io_axi1_write_data_valid);
BINDAXI(io_axi1_write_data_bits_data);
BINDAXI(io_axi1_write_data_bits_strb);
- BINDAXI(io_axi1_write_data_bits_id);
BINDAXI(io_axi1_write_data_bits_last);
BINDAXI(io_axi1_write_resp_ready);
BINDAXI(io_axi1_write_resp_valid);
diff --git a/tests/verilator_sim/kelvin/dbus2axi_tb.cc b/tests/verilator_sim/kelvin/dbus2axi_tb.cc
index 5587367..d9cb93d 100644
--- a/tests/verilator_sim/kelvin/dbus2axi_tb.cc
+++ b/tests/verilator_sim/kelvin/dbus2axi_tb.cc
@@ -47,7 +47,6 @@
sc_in<sc_bv<8> > io_axi_write_addr_bits_len;
sc_in<sc_bv<256> > io_axi_write_data_bits_data;
sc_in<sc_bv<32> > io_axi_write_data_bits_strb;
- sc_in<sc_bv<6> > io_axi_write_data_bits_id;
sc_in<bool> io_axi_write_data_bits_last;
sc_out<sc_bv<6> > io_axi_write_resp_bits_id;
sc_out<sc_bv<2> > io_axi_write_resp_bits_resp;
@@ -328,7 +327,6 @@
sc_signal<sc_bv<8> > io_axi_write_addr_bits_len;
sc_signal<sc_bv<256> > io_axi_write_data_bits_data;
sc_signal<sc_bv<32> > io_axi_write_data_bits_strb;
- sc_signal<sc_bv<6> > io_axi_write_data_bits_id;
sc_signal<bool> io_axi_write_data_bits_last;
sc_signal<sc_bv<6> > io_axi_write_resp_bits_id;
sc_signal<sc_bv<2> > io_axi_write_resp_bits_resp;
@@ -383,7 +381,6 @@
BIND2(tb, d2a, io_axi_write_addr_bits_len);
BIND2(tb, d2a, io_axi_write_data_bits_data);
BIND2(tb, d2a, io_axi_write_data_bits_strb);
- BIND2(tb, d2a, io_axi_write_data_bits_id);
BIND2(tb, d2a, io_axi_write_data_bits_last);
BIND2(tb, d2a, io_axi_write_resp_bits_id);
BIND2(tb, d2a, io_axi_write_resp_bits_resp);
diff --git a/tests/verilator_sim/kelvin/l1dcache_tb.cc b/tests/verilator_sim/kelvin/l1dcache_tb.cc
index bc9a345..f46836b 100644
--- a/tests/verilator_sim/kelvin/l1dcache_tb.cc
+++ b/tests/verilator_sim/kelvin/l1dcache_tb.cc
@@ -83,7 +83,6 @@
sc_out<bool> io_axi_write_data_ready;
sc_in<sc_bv<kL1DAxiStrb> > io_axi_write_data_bits_strb;
sc_in<sc_bv<kL1DAxiBits> > io_axi_write_data_bits_data;
- sc_in<sc_bv<kL1DAxiId - kDBusBankAdj> > io_axi_write_data_bits_id;
sc_in<bool> io_axi_write_data_bits_last;
sc_out<bool> io_axi_write_resp_valid;
@@ -492,7 +491,6 @@
sc_signal<bool> io_axi_write_data_ready;
sc_signal<sc_bv<kL1DAxiStrb> > io_axi_write_data_bits_strb;
sc_signal<sc_bv<kL1DAxiBits> > io_axi_write_data_bits_data;
- sc_signal<sc_bv<kL1DAxiId - kDBusBankAdj> > io_axi_write_data_bits_id;
sc_signal<bool> io_axi_write_data_bits_last;
sc_signal<bool> io_axi_write_resp_valid;
@@ -568,7 +566,6 @@
BIND2(tb, l1dcache, io_axi_write_data_ready);
BIND2(tb, l1dcache, io_axi_write_data_bits_strb);
BIND2(tb, l1dcache, io_axi_write_data_bits_data);
- BIND2(tb, l1dcache, io_axi_write_data_bits_id);
BIND2(tb, l1dcache, io_axi_write_data_bits_last);
BIND2(tb, l1dcache, io_axi_write_resp_valid);
diff --git a/tests/verilator_sim/kelvin/vst_tb.cc b/tests/verilator_sim/kelvin/vst_tb.cc
index b8fe457..1032f78 100644
--- a/tests/verilator_sim/kelvin/vst_tb.cc
+++ b/tests/verilator_sim/kelvin/vst_tb.cc
@@ -54,7 +54,6 @@
sc_in<sc_bv<8> > io_axi_addr_bits_len;
sc_in<sc_bv<kVector> > io_axi_data_bits_data;
sc_in<sc_bv<kUncStrb> > io_axi_data_bits_strb;
- sc_in<sc_bv<6> > io_axi_data_bits_id;
sc_in<bool> io_axi_data_bits_last;
sc_out<sc_bv<6> > io_axi_resp_bits_id;
sc_out<sc_bv<2> > io_axi_resp_bits_resp;
@@ -431,7 +430,6 @@
sc_signal<sc_bv<8> > io_axi_addr_bits_len;
sc_signal<sc_bv<kVector> > io_axi_data_bits_data;
sc_signal<sc_bv<kUncStrb> > io_axi_data_bits_strb;
- sc_signal<sc_bv<6> > io_axi_data_bits_id;
sc_signal<bool> io_axi_data_bits_last;
sc_signal<sc_bv<6> > io_axi_resp_bits_id;
sc_signal<sc_bv<2> > io_axi_resp_bits_resp;
@@ -509,7 +507,6 @@
BIND2(tb, st, io_axi_addr_bits_len);
BIND2(tb, st, io_axi_data_bits_data);
BIND2(tb, st, io_axi_data_bits_strb);
- BIND2(tb, st, io_axi_data_bits_id);
BIND2(tb, st, io_axi_data_bits_last);
BIND2(tb, st, io_axi_resp_bits_id);
BIND2(tb, st, io_axi_resp_bits_resp);
