commit | 350a35d5317b0b2b6dabda352f55c8ceca0768cc | [log] [tgz] |
---|---|---|
author | Derek Chow <derekjchow@google.com> | Thu Jul 10 12:49:24 2025 -0700 |
committer | Derek Chow <derekjchow@google.com> | Thu Jul 10 16:22:35 2025 -0700 |
tree | 3145449df2061e9ee8432d51b38eb44f96047a19 | |
parent | 653a90858c3b56db41c6d7f2c652c6b4fcd9584f [diff] |
Plumb rvv_idle output RvvCore. Change-Id: I6252637a06289e23027e4be4fd12dea5156c9a76
Kelvin is a RISC-V32IM core with a custom instruction set.
More information on the design can be found in the overview.
Kelvin uses bazel as it's build system. The Verilated simulator for Kelvin can be generated using:
bazel build //tests/verilator_sim:core_sim
The verilog source for the Kelvin core can be generated using:
bazel build //hdl/chisel/src/kelvin:core_cc_library_emit_verilog
Verilog source for the Matcha SoC can be generated using:
bazel clean --expunge # To generate the ToT sha bazel build //hdl/chisel:matcha_kelvin_verilog