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opensecura/build/c0e7aae1304f21d9c7822fa0e28172fd9e09349d^1..c0e7aae1304f21d9c7822fa0e28172fd9e09349d/.
commit
c0e7aae1304f21d9c7822fa0e28172fd9e09349d
[log]
author
Michael Hoang <hoangm@google.com>
Wed Sep 04 19:17:00 2024 +0000
committer
Gerrit Code Review <noreply-gerritcodereview@google.com>
Wed Sep 04 19:17:00 2024 +0000
tree
823be082e630e3588e43fd0ed57c0f84ac41889c
parent
99e71fe81a0b89a8595e42a0f8244b70fda7b08f [diff]
parent
b2f931db24b555ae34ecac37837a21ecd6610012 [diff]
Merge "Create separate matcha & sencha bitstream targets"
diff --git a/platforms/nexus/matcha_hw.mk b/platforms/nexus/matcha_hw.mk
index 53ee435..d670bf4 100644
--- a/platforms/nexus/matcha_hw.mk
+++ b/platforms/nexus/matcha_hw.mk

@@ -60,9 +60,9 @@
 # and Vivado suporting the latest UltraScale+ device to build it.
 matcha_hw_fpga_nexus: | $(MATCHA_OUT_DIR)
 	cd $(MATCHA_SRC_DIR) && \
-		bazel build //hw/bitstream/vivado:fpga_nexus
+		bazel build //hw/bitstream/vivado:matcha_fpga_nexus
 	cd $(MATCHA_SRC_DIR) && \
-		find bazel-bin/hw/bitstream/vivado/build.fpga_nexus/ -regex '.*.\(bit\|mmi\)' \
+		find bazel-bin/hw/bitstream/vivado/build.matcha_fpga_nexus/ -regex '.*.\(bit\|mmi\)' \
 			-exec cp -f '{}' "$(MATCHA_OUT_DIR)" \;
 
 $(MATCHA_TESTLOG_DIR):
@@ -146,9 +146,9 @@
 # out/matcha/hw/
 multihart_boot_rom:  | $(MATCHA_OUT_DIR)
 	cd $(MATCHA_SRC_DIR) && \
-		bazel build --config=riscv32 //sw/device/lib/testing/test_rom:test_rom_no_otp_fpga_nexus.elf
+		bazel build --config=riscv32 //sw/device/lib/testing/test_rom:matcha_test_rom_no_otp_fpga_nexus.elf
 	cd $(MATCHA_SRC_DIR) && \
-		find "bazel-out/" -wholename "*test_rom/test_rom_no_otp_fpga_nexus.elf" \
+		find "bazel-out/" -wholename "*test_rom/matcha_test_rom_no_otp_fpga_nexus.elf" \
 		-exec cp -f '{}' "$(MATCHA_OUT_DIR)/$(BOOT_ROM_ELF)" \;
 
 ## Clean Matcha HW artifact
@@ -173,7 +173,7 @@
 latest_bitstream: | $(OUT)
 	curl https://storage.googleapis.com/shodan-public-artifacts/nexus-bitstream_latest.tar.gz -o $(OUT)/nexus-bitstream.tar.gz
 	tar -C $(OUT) -xf $(OUT)/nexus-bitstream.tar.gz
-	tar -C $(OUT) -xf $(OUT)/results/fpga_nexus_smoketest.tar.gz
+	tar -C $(OUT) -xf $(OUT)/results/matcha_fpga_nexus_smoketest.tar.gz
 	curl https://storage.googleapis.com/shodan-public-artifacts/opentitantool_pkg_latest.tar.gz -o $(OUT)/opentitantool_pkg.tar.gz
 	tar -C $(OUT) -xf $(OUT)/opentitantool_pkg.tar.gz
 

diff --git a/platforms/nexus/sencha_hw.mk b/platforms/nexus/sencha_hw.mk
new file mode 100644
index 0000000..128d525
--- /dev/null
+++ b/platforms/nexus/sencha_hw.mk

@@ -0,0 +1,183 @@
+# Copyright 2024 Google LLC
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+#     https://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+
+SENCHA_SRC_DIR                := $(ROOTDIR)/hw/matcha
+SENCHA_OUT_DIR                := $(OUT)/sencha/hw
+SENCHA_VERILATOR_TB           := $(SENCHA_OUT_DIR)/sim-verilator/Vsencha_sim_tb
+SENCHA_TESTLOG_DIR            := $(SENCHA_OUT_DIR)/test-log
+SENCHA_FPGA_BINARY_DIR        := $(SENCHA_OUT_DIR)/fpga_tests
+SENCHA_FPGA_SENCHA_BINARY_DIR := $(SENCHA_FPGA_BINARY_DIR)/sencha
+SENCHA_FPGA_KELVIN_BINARY_DIR := $(SENCHA_FPGA_BINARY_DIR)/kelvin
+BOOT_ROM_ELF                  := boot_rom.elf
+
+$(SENCHA_OUT_DIR):
+	mkdir -p $(SENCHA_OUT_DIR)
+
+## Regenerate Sencha HW files frop IPs and top_sencha definition.
+# This target uses Open Titan's autogen tools as well as the HW IPs to generate
+# the system verilog files as well as the DV register definition cores and
+# system verilog files. The source code is from both hw/opentitan-upstream and
+# hw/sencha/, while the output is stored at out/sencha/hw.
+#
+# This is a dev-only target (not for CI), as it modifies the hw/sencha source
+# tree with generated code.
+sencha_hw_generate_all: | $(SENCHA_OUT_DIR)
+	$(MAKE) -C "$(SENCHA_SRC_DIR)/hw" TOPS=top_sencha all
+
+## Build Sencha verilator testbench.
+# This target builds the verilator testbench binary from hw/sencha using
+# hw/opentitan-upstream as the library. The output is stored in
+# out/sencha/hw/.
+# This target is compute-intensive. Make sure you have a powerful enough machine
+# to build it.
+sencha_hw_verilator_sim: $(SENCHA_VERILATOR_TB)
+
+$(SENCHA_VERILATOR_TB): $(SENCHA_OUT_DIR) verilator
+	cd $(SENCHA_SRC_DIR) && \
+		bazel build //hw:sencha_verilator
+	cd $(SENCHA_SRC_DIR) && \
+		cp -rf --no-preserve=mode bazel-bin/hw/build.sencha_verilator_real/* "$(SENCHA_OUT_DIR)" && \
+		chmod +x "$(SENCHA_OUT_DIR)/sim-verilator/Vsencha_sim_tb"
+
+## Build Sencha FPGA Target for Nexus Board.
+# This target builds the FPGA bit file from hw/sencha using
+# hw/opentitan-upstream as the library. The output is stored in
+# out/sencha/hw/.
+# This target is compute-intensive. Make sure you have a powerful enough machine
+# and Vivado suporting the latest UltraScale+ device to build it.
+sencha_hw_fpga_nexus: | $(SENCHA_OUT_DIR)
+	cd $(SENCHA_SRC_DIR) && \
+		bazel build //hw/bitstream/vivado:sencha_fpga_nexus
+	cd $(SENCHA_SRC_DIR) && \
+		find bazel-bin/hw/bitstream/vivado/build.sencha_fpga_nexus/ -regex '.*.\(bit\|mmi\)' \
+			-exec cp -f '{}' "$(SENCHA_OUT_DIR)" \;
+
+$(SENCHA_TESTLOG_DIR):
+	mkdir -p $(SENCHA_TESTLOG_DIR)
+
+## Build Sencha sw artifacts
+#
+# Checks the sencha sw code integrity for targets not covered by the verilator
+# tests.
+#
+sencha_sw_all: | $(SENCHA_OUT_DIR)
+	cd $(SENCHA_SRC_DIR) && \
+	  bazel build --define DISABLE_VERILATOR_BUILD=true --build_tag_filters="-kelvin_fpga" \
+			//sw/device/...
+	cd $(SENCHA_SRC_DIR) && \
+	  find "bazel-out/" \( -type f -name "*.elf" -o -name "*.bin" -o -name "*.vmem" \) \
+		-exec cp -f --parents "{}" "$(SENCHA_OUT_DIR)" \;
+
+$(SENCHA_FPGA_SENCHA_BINARY_DIR):
+	mkdir -p $(SENCHA_FPGA_SENCHA_BINARY_DIR)
+
+## Build test binaries that run on FPGA
+sencha_fpga_tests: | $(SENCHA_FPGA_SENCHA_BINARY_DIR)
+	cd $(SENCHA_SRC_DIR) && \
+		bazel query //sw/device/tests/... \
+			| grep 'fpga_nexus' \
+			| egrep '_bin$$' \
+			| grep -v '/smc:' \
+			| grep -v 'kelvin' \
+			| grep -v 'example_test_from_rom_rom_prog_fpga_nexus_bin' \
+			| xargs bazel build
+	cd $(SENCHA_SRC_DIR) && \
+		find 'bazel-out/' \
+			-type f \
+			\( -wholename "*ST-*/*fpga_nexus.elf" -o -wholename "*ST-*/*fpga_nexus.bin" \) \
+			-exec cp -f '{}' "$(SENCHA_FPGA_SENCHA_BINARY_DIR)" \;
+
+$(SENCHA_FPGA_KELVIN_BINARY_DIR):
+	mkdir -p "$(SENCHA_FPGA_KELVIN_BINARY_DIR)"
+
+
+## Build Sencha Kelvin SW FPGA test artifacts
+#
+# Build kelvin artifacts and package it in a tarball and ready for use on the FPGA
+# The output is at out/sencha/hw/fpga_tests/kelvin
+#
+sencha_kelvin_fpga_tarballs: kelvin_sw | $(SENCHA_FPGA_KELVIN_BINARY_DIR)
+	cd $(SENCHA_SRC_DIR) && \
+	  bazel build --define DISABLE_VERILATOR_BUILD=true \
+			@kelvin-binary//...
+# Copy the tarballs and sc binary to out/.
+	cd $(SENCHA_SRC_DIR) && \
+		find "bazel-out/" -type f -wholename "*fastbuild-*/sw/device/tests/kelvin/fpga_tests/kelvin_test_sc_extflash_fpga_nexus.bin" |\
+			xargs -I {} cp -f {} "$(SENCHA_FPGA_KELVIN_BINARY_DIR)"
+	cd $(SENCHA_SRC_DIR) && \
+		find "bazel-bin/external/kelvin-binary" -name "*.tar" |\
+			xargs -I {} cp -f {} "$(SENCHA_FPGA_KELVIN_BINARY_DIR)"
+
+
+## Build opentitantool for sencha FPGA tests
+opentitantool_pkg: | $(SENCHA_OUT_DIR)
+	cd $(SENCHA_SRC_DIR) && \
+	  bazel build //sw:opentitantool_pkg
+	cd $(SENCHA_SRC_DIR) && \
+		cp -f bazel-bin/sw/opentitantool_pkg.tar.gz $(SENCHA_OUT_DIR)
+
+## Build and run sencha verilator test suite
+#
+sencha_hw_verilator_tests: verilator | $(SENCHA_TESTLOG_DIR)
+	cd $(SENCHA_SRC_DIR) && \
+		bazel test --test_output=errors --test_timeout=180,600,1800,3600 \
+			--local_test_jobs=HOST_CPUS*0.25 \
+			--//hw:make_options=-j,16 \
+			//sw/device/tests:verilator_test_suite
+	cd $(SENCHA_SRC_DIR) && cp -rf "bazel-testlogs/sw" "$(SENCHA_TESTLOG_DIR)"
+
+## Build the boot ROM image
+#
+# This builds the HW boot rom executable for simulation.
+# Source is in hw/sencha, while output is placed in
+# out/sencha/hw/
+multihart_boot_rom:  | $(SENCHA_OUT_DIR)
+	cd $(SENCHA_SRC_DIR) && \
+		bazel build --config=riscv32 //sw/device/lib/testing/test_rom:sencha_test_rom_no_otp_fpga_nexus.elf
+	cd $(SENCHA_SRC_DIR) && \
+		find "bazel-out/" -wholename "*test_rom/sencha_test_rom_no_otp_fpga_nexus.elf" \
+		-exec cp -f '{}' "$(SENCHA_OUT_DIR)/$(BOOT_ROM_ELF)" \;
+
+## Clean Sencha HW artifact
+sencha_hw_clean:
+	rm -rf $(SENCHA_OUT_DIR)
+	cd $(SENCHA_SRC_DIR) && \
+		bazel clean --expunge
+
+## Build the spi_passthough binary
+#
+# This builds the spi_passthrough_fpga_nexus.bin binary that can be used to
+# write flash tarballs to the nexus SPI boot flash. The binary will be copied
+# to out/spi_passthrough_fpga_nexus.bin
+spi_passthrough: | $(OUT)
+	cd $(SENCHA_SRC_DIR) && \
+	  bazel build --define DISABLE_VERILATOR_BUILD=true \
+		sw/device/examples/spi_passthrough
+	find "$(SENCHA_SRC_DIR)/bazel-out/" -type f -wholename "*fastbuild-*/sw/device/examples/spi_passthrough/spi_passthrough_fpga_nexus.bin" |\
+			xargs -I '{}' cp -f '{}' "$(OUT)"
+
+## Fetch latest Nexus bitstream and matching opentitantool
+latest_bitstream: | $(OUT)
+	curl https://storage.googleapis.com/shodan-public-artifacts/nexus-bitstream_latest.tar.gz -o $(OUT)/nexus-bitstream.tar.gz
+	tar -C $(OUT) -xf $(OUT)/nexus-bitstream.tar.gz
+	tar -C $(OUT) -xf $(OUT)/results/sencha_fpga_nexus_smoketest.tar.gz
+	curl https://storage.googleapis.com/shodan-public-artifacts/opentitantool_pkg_latest.tar.gz -o $(OUT)/opentitantool_pkg.tar.gz
+	tar -C $(OUT) -xf $(OUT)/opentitantool_pkg.tar.gz
+
+.PHONY:: sencha_hw_verilator_sim sencha_hw_clean sencha_hw_verilator_tests
+.PHONY:: sencha_sw_all opentitantool_pkg
+.PHONY:: sencha_hw_fpga_nexus sencha_kelvin_fpga_tarballs
+.PHONY:: multihart_boot_rom
+.PHONY:: spi_passthrough
+.PHONY:: latest_bitstream

diff --git a/platforms/nexus/setup.sh b/platforms/nexus/setup.sh
index c1a2caa..a075e7f 100644
--- a/platforms/nexus/setup.sh
+++ b/platforms/nexus/setup.sh

@@ -261,9 +261,9 @@
     if [[ -z "${bitstream_path}" ]]; then
         (
             echo "WARNING: No bitstream specified. Loading default bitstream"
-            echo "from \$OUT/hw/bitstream/vivado/fpga_nexus_mask_test_rom.bit"
+            echo "from \$OUT/hw/bitstream/vivado/matcha_fpga_nexus_mask_test_rom.bit"
         ) | fmt
-        bitstream_path="${OUT}/hw/bitstream/vivado/fpga_nexus_mask_test_rom.bit"
+        bitstream_path="${OUT}/hw/bitstream/vivado/matcha_fpga_nexus_mask_test_rom.bit"
     fi
 
     if [[ -z "${NEXUS_ID}" ]]; then

diff --git a/platforms/shodan/matcha_hw.mk b/platforms/shodan/matcha_hw.mk
index 3568c4a..dd01e68 100644
--- a/platforms/shodan/matcha_hw.mk
+++ b/platforms/shodan/matcha_hw.mk

@@ -59,9 +59,9 @@
 # and Vivado suporting the latest UltraScale+ device to build it.
 matcha_hw_fpga_nexus: | $(MATCHA_OUT_DIR)
 	cd $(MATCHA_SRC_DIR) && \
-		bazel build //hw/bitstream/vivado:fpga_nexus
+		bazel build //hw/bitstream/vivado:matcha_fpga_nexus
 	cd $(MATCHA_SRC_DIR) && \
-		find bazel-bin/hw/bitstream/vivado/build.fpga_nexus/ -regex '.*.\(bit\|mmi\)' \
+		find bazel-bin/hw/bitstream/vivado/build.matcha_fpga_nexus/ -regex '.*.\(bit\|mmi\)' \
 			-exec cp -f '{}' "$(MATCHA_OUT_DIR)" \;
 
 $(MATCHA_TESTLOG_DIR):
@@ -127,9 +127,9 @@
 # out/matcha/hw/
 multihart_boot_rom:  | $(MATCHA_OUT_DIR)
 	cd $(MATCHA_SRC_DIR) && \
-		bazel build --config=riscv32 //sw/device/lib/testing/test_rom:test_rom_no_otp_fpga_nexus.elf
+		bazel build --config=riscv32 //sw/device/lib/testing/test_rom:matcha_test_rom_no_otp_fpga_nexus.elf
 	cd $(MATCHA_SRC_DIR) && \
-		find "bazel-out/" -wholename "*test_rom/test_rom_no_otp_fpga_nexus.elf" \
+		find "bazel-out/" -wholename "*test_rom/matcha_test_rom_no_otp_fpga_nexus.elf" \
 		-exec cp -f '{}' "$(MATCHA_OUT_DIR)/$(BOOT_ROM_ELF)" \;
 
 ## Clean Matcha HW artifact

diff --git a/platforms/shodan/sencha_hw.mk b/platforms/shodan/sencha_hw.mk
index a5edb46..e40eea9 100644
--- a/platforms/shodan/sencha_hw.mk
+++ b/platforms/shodan/sencha_hw.mk

@@ -56,12 +56,11 @@
 # This target is compute-intensive. Make sure you have a powerful enough machine
 # and Vivado suporting the latest UltraScale+ device to build it.
 #
-# TODO(hoangm): Change below target once the Sencha-specific bitstream target is supported.
 sencha_hw_fpga_nexus: | $(SENCHA_OUT_DIR)
 	cd $(SENCHA_SRC_DIR) && \
-		bazel build //hw/bitstream/vivado:fpga_nexus
+		bazel build //hw/bitstream/vivado:sencha_fpga_nexus
 	cd $(SENCHA_SRC_DIR) && \
-		find bazel-bin/hw/bitstream/vivado/build.fpga_nexus/ -regex '.*.\(bit\|mmi\)' \
+		find bazel-bin/hw/bitstream/vivado/build.sencha_fpga_nexus/ -regex '.*.\(bit\|mmi\)' \
 			-exec cp -f '{}' "$(SENCHA_OUT_DIR)" \;
 
 $(SENCHA_TESTLOG_DIR):

diff --git a/platforms/sparrow/matcha_hw.mk b/platforms/sparrow/matcha_hw.mk
index 6dc6f91..6422fae 100644
--- a/platforms/sparrow/matcha_hw.mk
+++ b/platforms/sparrow/matcha_hw.mk

@@ -133,9 +133,9 @@
 # out/matcha/hw/
 multihart_boot_rom:  | $(MATCHA_OUT_DIR)
 	cd $(MATCHA_SRC_DIR) && \
-		bazel build --config=riscv32 //sw/device/lib/testing/test_rom:test_rom_no_otp_asic.elf
+		bazel build --config=riscv32 //sw/device/lib/testing/test_rom:matcha_test_rom_no_otp_asic.elf
 	cd $(MATCHA_SRC_DIR) && \
-		find "bazel-out/" -wholename "*test_rom/test_rom_no_otp_asic.elf" \
+		find "bazel-out/" -wholename "*test_rom/matcha_test_rom_no_otp_asic.elf" \
 		-exec cp -f '{}' "$(MATCHA_OUT_DIR)/$(BOOT_ROM_ELF)" \;
 
 ## Clean Matcha HW artifact