Add sencha targets - Supports top_sencha as a verilator target. Currently does not support sencha-specific binaries in sw/ - Similar to matcha_hw.mk with the key differences being top_sencha passed as an arg to $TOPS for autogen flow and outputs stored in out/sencha Bypass-Presubmit-Reason: manually tested non-TODO items Change-Id: I4556ef03329130548e2d431fa8e3bbc8d61861bd
diff --git a/platforms/nexus/matcha_hw.mk b/platforms/nexus/matcha_hw.mk index 624988b..e753965 100644 --- a/platforms/nexus/matcha_hw.mk +++ b/platforms/nexus/matcha_hw.mk
@@ -47,7 +47,7 @@ # TODO(ykwang): Revise the structure of matcha output directory. $(MATCHA_VERILATOR_TB): $(MATCHA_OUT_DIR) verilator cd $(MATCHA_SRC_DIR) && \ - bazel build //hw:verilator + bazel build //hw:matcha_verilator cd $(MATCHA_SRC_DIR) && \ cp -rf --no-preserve=mode bazel-bin/hw/build.verilator_real/* "$(MATCHA_OUT_DIR)" && \ chmod +x "$(MATCHA_OUT_DIR)/sim-verilator/Vchip_sim_tb" @@ -182,4 +182,4 @@ .PHONY:: matcha_hw_fpga_nexus matcha_kelvin_fpga_tarballs .PHONY:: multihart_boot_rom .PHONY:: spi_passthrough -.PHONY:: latest_bitstream \ No newline at end of file +.PHONY:: latest_bitstream
diff --git a/platforms/shodan/matcha_hw.mk b/platforms/shodan/matcha_hw.mk index 443e8f5..6d726f7 100644 --- a/platforms/shodan/matcha_hw.mk +++ b/platforms/shodan/matcha_hw.mk
@@ -46,9 +46,9 @@ # TODO(ykwang): Revise the structure of matcha output directory. $(MATCHA_VERILATOR_TB): $(MATCHA_OUT_DIR) verilator cd $(MATCHA_SRC_DIR) && \ - bazel build //hw:verilator + bazel build //hw:matcha_verilator cd $(MATCHA_SRC_DIR) && \ - cp -rf --no-preserve=mode bazel-bin/hw/build.verilator_real/* "$(MATCHA_OUT_DIR)" && \ + cp -rf --no-preserve=mode bazel-bin/hw/build.matcha_verilator_real/* "$(MATCHA_OUT_DIR)" && \ chmod +x "$(MATCHA_OUT_DIR)/sim-verilator/Vchip_sim_tb" ## Build Matcha FPGA Target for Nexus Board.
diff --git a/platforms/shodan/platform.mk b/platforms/shodan/platform.mk index 5e898da..1b1956e 100644 --- a/platforms/shodan/platform.mk +++ b/platforms/shodan/platform.mk
@@ -18,6 +18,7 @@ include $(ROOTDIR)/build/platforms/shodan/opentitan_hw.mk include $(ROOTDIR)/build/platforms/shodan/opentitan_sw.mk include $(ROOTDIR)/build/platforms/shodan/springbok.mk +include $(ROOTDIR)/build/platforms/shodan/sencha_hw.mk include $(ROOTDIR)/build/platforms/shodan/tbm.mk include $(ROOTDIR)/build/platforms/shodan/tock.mk
diff --git a/platforms/shodan/sencha_hw.mk b/platforms/shodan/sencha_hw.mk new file mode 100644 index 0000000..a5edb46 --- /dev/null +++ b/platforms/shodan/sencha_hw.mk
@@ -0,0 +1,122 @@ +# Copyright 2024 Google LLC +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# https://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. + +SENCHA_SRC_DIR := $(ROOTDIR)/hw/matcha +SENCHA_OUT_DIR := $(OUT)/sencha/hw +SENCHA_VERILATOR_TB := $(SENCHA_OUT_DIR)/sim-verilator/Vsencha_sim_tb +SENCHA_TESTLOG_DIR := $(SENCHA_OUT_DIR)/test-log +SENCHA_FPGA_BINARY_DIR := $(SENCHA_OUT_DIR)/fpga_tests +SENCHA_FPGA_KELVIN_BINARY_DIR := $(SENCHA_FPGA_BINARY_DIR)/kelvin + +$(SENCHA_OUT_DIR): + mkdir -p $(SENCHA_OUT_DIR) + +## Regenerate Sencha HW files frop IPs and top_sencha definition. +# This target uses Open Titan's autogen tools as well as the HW IPs to generate +# the system verilog files as well as the DV register definition cores and +# system verilog files. The source code is from both hw/opentitan-upstream and +# hw/matcha/, while the output is stored at out/sencha/hw. +# +# This is a dev-only target (not for CI), as it modifies the hw/sencha source +# tree with generated code. + +sencha_hw_generate_all: | $(SENCHA_OUT_DIR) + $(MAKE) -C "$(SENCHA_SRC_DIR)/hw" TOPS=top_sencha all + +## Build Sencha verilator testbench. +# This target builds the verilator testbench binary from hw/matcha/hw/top_sencha +# using hw/matcha/hw/ip and hw/opentitan-upstream as the libraries. The output is +# stored in out/sencha/hw/. +# This target is compute-intensive. Make sure you have a powerful enough machine +# to build it. +sencha_hw_verilator_sim: $(SENCHA_VERILATOR_TB) + +$(SENCHA_VERILATOR_TB): $(SENCHA_OUT_DIR) verilator + cd $(SENCHA_SRC_DIR) && \ + bazel build //hw:sencha_verilator + cd $(SENCHA_SRC_DIR) && \ + cp -rf --no-preserve=mode bazel-bin/hw/build.sencha_verilator_real/* "$(SENCHA_OUT_DIR)" && \ + chmod +x "$(SENCHA_OUT_DIR)/sim-verilator/Vsencha_sim_tb" + +## Build Sencha FPGA Target for Nexus Board. +# This target builds the FPGA bit file from hw/sencha using +# hw/opentitan-upstream as the library. The output is stored in +# out/sencha/hw/. +# This target is compute-intensive. Make sure you have a powerful enough machine +# and Vivado suporting the latest UltraScale+ device to build it. +# +# TODO(hoangm): Change below target once the Sencha-specific bitstream target is supported. +sencha_hw_fpga_nexus: | $(SENCHA_OUT_DIR) + cd $(SENCHA_SRC_DIR) && \ + bazel build //hw/bitstream/vivado:fpga_nexus + cd $(SENCHA_SRC_DIR) && \ + find bazel-bin/hw/bitstream/vivado/build.fpga_nexus/ -regex '.*.\(bit\|mmi\)' \ + -exec cp -f '{}' "$(SENCHA_OUT_DIR)" \; + +$(SENCHA_TESTLOG_DIR): + mkdir -p $(SENCHA_TESTLOG_DIR) + +## Build Sencha sw artifacts +# +# Checks the sencha sw code integrity for targets not covered by the verilator +# tests. +# +# TODO(hoangm): Change below target to test Sencha-specific target once CHERIoT binaries can be +# built. Currently the target builds matcha targets as well. +sencha_sw_all: | $(SENCHA_OUT_DIR) + cd $(SENCHA_SRC_DIR) && \ + bazel build --define DISABLE_VERILATOR_BUILD=true --build_tag_filters="-kelvin_fpga" \ + //sw/device/... + cd $(SENCHA_SRC_DIR) && \ + find "bazel-out/" \( -type f -name "*.elf" -o -name "*.bin" -o -name "*.vmem" \) \ + -exec cp -f --parents "{}" "$(SENCHA_OUT_DIR)" \; + + +$(SENCHA_FPGA_KELVIN_BINARY_DIR): + mkdir -p "$(SENCHA_FPGA_KELVIN_BINARY_DIR)" + + +## Build Sencha Kelvin SW FPGA test artifacts +# +# Build kelvin artifacts and package it in a tarball and ready for use on the FPGA +# The output is at out/sencha/hw/fpga_tests/kelvin +# +sencha_kelvin_fpga_tarballs: kelvin_sw | $(SENCHA_FPGA_KELVIN_BINARY_DIR) + cd $(SENCHA_SRC_DIR) && \ + bazel build --define DISABLE_VERILATOR_BUILD=true \ + @kelvin-binary//... +# Copy the tarballs and sc binary to out/. + cd $(SENCHA_SRC_DIR) && \ + find "bazel-out/" -type f -wholename "*fastbuild-*/sw/device/tests/kelvin/fpga_tests/kelvin_test_sc_extflash_fpga_nexus.bin" |\ + xargs -I {} cp -f {} "$(SENCHA_FPGA_KELVIN_BINARY_DIR)" + cd $(SENCHA_SRC_DIR) && \ + find "bazel-bin/external/kelvin-binary" -name "*.tar" |\ + xargs -I {} cp -f {} "$(SENCHA_FPGA_KELVIN_BINARY_DIR)" + + +## Build and run sencha verilator test suite +# +# TODO(hoangm): Change below target to test Sencha-specific target once CHERIoT binaries can be +# built. Currently the target builds matcha targets. +sencha_hw_verilator_tests: verilator | $(SENCHA_TESTLOG_DIR) + cd $(SENCHA_SRC_DIR) && \ + bazel test --test_output=errors --test_timeout=180,600,1800,3600 \ + --local_test_jobs=HOST_CPUS*0.25 \ + --//hw:make_options=-j,16 \ + //sw/device/tests:verilator_test_suite + cd $(SENCHA_SRC_DIR) && cp -rf "bazel-testlogs/sw" "$(SENCHA_TESTLOG_DIR)" + +.PHONY:: sencha_hw_verilator_sim sencha_hw_verilator_tests +.PHONY:: sencha_sw_all +.PHONY:: sencha_hw_fpga_nexus sencha_kelvin_fpga_tarballs
diff --git a/platforms/sparrow/matcha_hw.mk b/platforms/sparrow/matcha_hw.mk index 73af09b..863cd66 100644 --- a/platforms/sparrow/matcha_hw.mk +++ b/platforms/sparrow/matcha_hw.mk
@@ -47,7 +47,7 @@ # TODO(ykwang): Revise the structure of matcha output directory. $(MATCHA_VERILATOR_TB): $(MATCHA_OUT_DIR) verilator cd $(MATCHA_SRC_DIR) && \ - bazel build //hw:verilator + bazel build //hw:matcha_verilator cd $(MATCHA_SRC_DIR) && \ cp -rf --no-preserve=mode bazel-bin/hw/build.verilator_real/* "$(MATCHA_OUT_DIR)" && \ chmod +x "$(MATCHA_OUT_DIR)/sim-verilator/Vchip_sim_tb" @@ -166,4 +166,4 @@ .PHONY:: matcha_kelvin_asic_tarballs .PHONY:: multihart_boot_rom .PHONY:: spi_passthrough -.PHONY:: latest_opentitantool \ No newline at end of file +.PHONY:: latest_opentitantool