Merge pull request #140 from oxidecomputer/clobber-fix

Change RISC-V register names in clobbers.

src/entry_point/start_item_riscv32.rs

diff --git a/src/entry_point/start_item_riscv32.rs b/src/entry_point/start_item_riscv32.rs
index c107f36..cabfd66 100644
--- a/src/entry_point/start_item_riscv32.rs
+++ b/src/entry_point/start_item_riscv32.rs
@@ -93,8 +93,8 @@
     jal  rust_start"
     :                                                              // No output operands
     :
-    : "memory", "a0", "a1", "a2", "a3", "a4", "a5", "a6", "a7",
-      "t0", "t1", "t2", "t3", "t4", "t5", "t6", "ra"               // Clobbers
+    : "memory", "x10", "x11", "x12", "x13", "x14", "x15", "x16", "x17",
+      "x5", "x6", "x7", "x28", "x29", "x30", "x31", "x1"           // Clobbers
     : "volatile"                                                   // Options
     );
     hint::unreachable_unchecked();

src/syscalls/platform_riscv32.rs

diff --git a/src/syscalls/platform_riscv32.rs b/src/syscalls/platform_riscv32.rs
index 88ddeec..f7d1858 100644
--- a/src/syscalls/platform_riscv32.rs
+++ b/src/syscalls/platform_riscv32.rs
@@ -8,8 +8,8 @@
             ecall"
             :
             :
-            : "memory", "a0", "a1", "a2", "a3", "a4", "a5", "a6", "a7",
-            "t0", "t1", "t2", "t3", "t4", "t5", "t6", "ra"
+            : "memory", "x10", "x11", "x12", "x13", "x14", "x15", "x16", "x17",
+            "x5", "x6", "x7", "x28", "x29", "x30", "x31", "x1"
             : "volatile");
 }