| commit | 2f97d82192974e1129d6b2352dea17ad7bf27712 | [log] [tgz] |
|---|---|---|
| author | RJ Ascani <rjascani@google.com> | Thu Nov 30 14:21:00 2023 -0800 |
| committer | GitHub <noreply@github.com> | Thu Nov 30 22:21:00 2023 +0000 |
| tree | 29a8b0be5c50433907bb2d0eea8b94aa4929dfe5 | |
| parent | c1a5f16129afbfa057988d3ded31456aa68feb6d [diff] |
Initialize ArithmeticParams & OpDataReduce (#2337) There are several structs that are allocated as either part of the arena or on the stack that do not get entirely initialized. It is typical that individual operations will just fill in the fields of a struct that they need. This can lead to difficult to find bugs where a field is used despite never being initialized. This PR resolves two such instances found in issue #2336. The first is in the reference ADD kernel, where we use ArithmeticParams without initializing it. This is resolved by zero initializing the struct when it is declared. The second is the OpDataReduce object that is created in the Persistent Arena for Reduce kernels. This is resolved by performing placement new on the buffer that is returned from AllocatePersistentBuffer. This is a pattern we use elsewhere with allocations, and likely one we should re-use in all Init functions. BUG=#2336
TensorFlow Lite for Microcontrollers is a port of TensorFlow Lite designed to run machine learning models on DSPs, microcontrollers and other devices with limited memory.
Additional Links:
| Build Type | Status |
|---|---|
| CI (Linux) |  |
| Code Sync |  |
This table captures platforms that TFLM has been ported to. Please see New Platform Support for additional documentation.
| Platform | Status |
|---|---|
| Arduino |   |
| Coral Dev Board Micro | TFLM + EdgeTPU Examples for Coral Dev Board Micro |
| Espressif Systems Dev Boards |  |
| Renesas Boards | TFLM Examples for Renesas Boards |
| Silicon Labs Dev Kits | TFLM Examples for Silicon Labs Dev Kits |
| Sparkfun Edge |  |
| Texas Instruments Dev Boards |  |
This is a list of targets that have optimized kernel implementations and/or run the TFLM unit tests using software emulation or instruction set simulators.
| Build Type | Status |
|---|---|
| Cortex-M |  |
| Hexagon |  |
| RISC-V |  |
| Xtensa |  |
| Generate Integration Test |  |
See our contribution documentation.
A Github issue should be the primary method of getting in touch with the TensorFlow Lite Micro (TFLM) team.
The following resources may also be useful:
SIG Micro email group and monthly meetings.
SIG Micro gitter chat room.
For questions that are not specific to TFLM, please consult the broader TensorFlow project, e.g.: