commit 673aeac16d43f17c4227c6c23b8a8f3d8b0bc9f2
author June Tate-Gans <jtgans@google.com> Thu Oct 22 20:03:20 2020 +0000
committer June Tate-Gans <jtgans@google.com> Thu Oct 22 20:03:20 2020 +0000
tree 6547fe4cd115b68987a56ea16fb080715f258040
parent 70dd9243456da78d030fa13af6642ba080b703a2

riscv: Fix sel4bench.h macros to be valid C

The sel4bench.h header macros were invalid C code and would not compile
using spike as the platform and rv32 as the architecture.

libsel4bench/arch_include/riscv/sel4bench/arch/sel4bench.h

diff --git a/libsel4bench/arch_include/riscv/sel4bench/arch/sel4bench.h b/libsel4bench/arch_include/riscv/sel4bench/arch/sel4bench.h
index c0591ac..9882aa0 100644
--- a/libsel4bench/arch_include/riscv/sel4bench/arch/sel4bench.h
+++ b/libsel4bench/arch_include/riscv/sel4bench/arch/sel4bench.h
@@ -20,17 +20,18 @@
 #define FASTFN inline __attribute__((always_inline))
 
 #if __riscv_xlen == 32
-#define SEL4BENCH_READ_CCNT(var) \
+#define SEL4BENCH_READ_CCNT(var) {              \
     uint32_t nH1, nL, nH2; \
     asm volatile("rdcycleh %0\n" \
                  "rdcycle %1\n" \
                  "rdcycleh %2\n" \
                  : "=r"(nH1), "=r"(nL), "=r"(nH2)); \
     if (nH1 < nH2) { \
-        asm volatile("rdcycle %0" : "=r"(nL); \
+      asm volatile("rdcycle %0" : "=r"(nL));    \
         nH1 = nH2; \
     } \
-    var = ((uint64_t)((uint64_t) nH1 << 32 | (nL);
+    var = ((uint64_t)((uint64_t) nH1 << 32 | (nL))); \
+    }
 #else
 #define SEL4BENCH_READ_CCNT(var) \
     asm volatile("rdcycle %0" :"=r"(var));
@@ -41,17 +42,18 @@
 } while(0)
 
 #if __riscv_xlen == 32
-#define SEL4BENCH_READ_PCNT(idx, var) \
+#define SEL4BENCH_READ_PCNT(idx, var) {         \
     uint32_t nH1, nL, nH2; \
     asm volatile("csrr %0, hpmcounterh" #idx \
                  "csrr %1, hpmcounter" #idx \
                  "csrr %2, hpmcounterh" #idx \
                  : "=r"(nH1), "=r"(nL), "=r"(nH2)); \
     if (nH1 < nH2) { \
-        asm volatile("csrr %0, hpmcounter" #idx : "=r"(nL); \
-        nH1 = nH2; \
+      asm volatile("csrr %0, hpmcounter" #idx : "=r"(nL));  \
+      nH1 = nH2;                                            \
     } \
-    var = ((uint64_t)((uint64_t) nH1 << 32 | (nL);
+      var = ((uint64_t)((uint64_t) nH1 << 32 | (nL))); \
+      }
 #else
 #define SEL4BENCH_READ_PCNT(idx, var) \
     asm volatile("csrr %0, hpmcounter" #idx : "=r"(var));