commit 1f177036a60d8b473a9c3ffc3858a62e73c2e224
author Siwei Zhuang <siwei.zhuang@data61.csiro.au> Thu Mar 26 16:42:29 2020 +1100
committer Siwei Zhuang <siwei.zhuang@data61.csiro.au> Thu Mar 26 16:49:55 2020 +1100
tree 64fb70bb0e379f18ddf138e97a844a310afe3187
parent 8fbe6c089edc4f9cb02a6d31402055158bc2b6d8

libsel4bench: Use privileged HPM counter CSRs

This change is a work around for some Hifive boards which would freeze
when accessing user mode CSRs.

libsel4bench/arch_include/riscv/sel4bench/arch/sel4bench.h

diff --git a/libsel4bench/arch_include/riscv/sel4bench/arch/sel4bench.h b/libsel4bench/arch_include/riscv/sel4bench/arch/sel4bench.h
index 61fe70b..c0591ac 100644
--- a/libsel4bench/arch_include/riscv/sel4bench/arch/sel4bench.h
+++ b/libsel4bench/arch_include/riscv/sel4bench/arch/sel4bench.h
@@ -150,18 +150,18 @@
 
         /* Reset and start the counter*/
 #if __riscv_xlen == 32
-        asm volatile("csrw hpmcounterh3, 0");
+        asm volatile("csrw mhpmcounterh3, 0");
 #endif
-        asm volatile("csrw hpmcounter3, 0\n"
+        asm volatile("csrw mhpmcounter3, 0\n"
                      "csrw mhpmevent3, %0\n"
                      :: "r"(event));
         break;
     case 1:
         asm volatile("csrw mhpmevent4, 0");
 #if __riscv_xlen == 32
-        asm volatile("csrw hpmcounterh4, 0");
+        asm volatile("csrw mhpmcounterh4, 0");
 #endif
-        asm volatile("csrw hpmcounter4, 0\n"
+        asm volatile("csrw mhpmcounter4, 0\n"
                      "csrw mhpmevent4, %0\n"
                      :: "r"(event));
         break;